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Article

VLSI-Friendly Filtering Algorithms for Deep Neural Networks

Faculty of Computer Science and Information Technology, West Pomeranian University of Technology in Szczecin, Żołnierska 49, 71-210 Szczecin, Poland
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Author to whom correspondence should be addressed.
Appl. Sci. 2023, 13(15), 9004; https://doi.org/10.3390/app13159004
Submission received: 5 July 2023 / Revised: 31 July 2023 / Accepted: 4 August 2023 / Published: 6 August 2023
(This article belongs to the Special Issue Recent Developments in Algorithms and Computational Complexity)

Abstract

:
The paper introduces a range of efficient algorithmic solutions for implementing the fundamental filtering operation in convolutional layers of convolutional neural networks on fully parallel hardware. Specifically, these operations involve computing M inner products between neighbouring vectors generated by a sliding time window from the input data stream and an M-tap finite impulse response filter. By leveraging the factorisation of the Hankel matrix, we have successfully reduced the multiplicative complexity of the matrix-vector product calculation. This approach has been applied to develop fully parallel and resource-efficient algorithms for M values of 3, 5, 7, and 9. The fully parallel hardware implementation of our proposed algorithms achieves approximately a 30% reduction in embedded multipliers compared to the naive calculation methods.

1. Introduction

The need for high-speed processing of large amounts of information stimulates the development and use of highly effective data processing systems. In such systems, the primary requirement for implementing computing methods is to minimise the time of data processing, ensuring the ability to fulfil the planned task within the allocated time for this application. This requirement is especially relevant in the implementation of algorithms for processing digital information in deep neural networks (DNNs) [1,2,3,4,5]. As is known, in deep neural networks, the primary and time-consuming operation is digital convolution. The need to quickly calculate digital convolution arises in both convolutional and capsule neural networks. Digital convolution calculations can be accelerated by algorithmic and hardware methods. In general, algorithmic methods primarily focus on minimising the number of arithmetic operations involved. One widely employed strategy for reducing the computational complexity of the digital convolution operation is utilising the Fast Fourier Transform (FFT) algorithm. This approach has found application in some deep neural networks [6,7,8,9,10,11]. However, modern convolutional and capsule neural networks use small filters more often than the traditionally used large filters computed using the FFT approach. The Winograd’s minimal filtering algorithm [1,12,13,14,15], which has recently gained significant popularity, is widely regarded as well-suited for such scenarios. This approach exhibits enhanced efficiency, specifically when employing small filters and tile sizes. In such cases, it performs linear convolution with minimal computational complexity. Indeed, this method calculates the dot products of adjacent vectors obtained from a sliding time window in the current data stream. It employs a third-order finite impulse response filter (FIR) for this purpose.

2. State of the Art

Since we are talking mainly about convolutional and capsular neural networks, it is clear that linear convolution is the main operation in their implementation. In general, convolutional layers tend to be the most time-intensive component, often accounting for over half of the total computation time in a typical implementation [16,17]. The convolution itself is also a time-consuming operation. For this reason, deep neural network builders are looking for and creating efficient ways to minimise convolution computation complexity [11].
Another opportunity to speed up calculations in deep neural networks is by utilising high-performance field-programmable gate arrays (FPGAs) [18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33], graphics processing units (GPUs) [33,34,35,36], and specialised application-specific integrated circuits (ASICs) [33,37,38,39].
When modern stationary data processing systems possess ample computing power, the design of mobile on-board systems powered by batteries encounters various conflicting factors that hinder peak performance. The conventional approach of parallelising computations to enhance data processing speed increases the data processing unit’s size, weight, and power consumption. Consequently, there is a necessity for solutions that effectively leverage computational parallelisation while concurrently optimising hardware costs.
Extensive research is being conducted on algorithms and structures for high-performance computing devices intended to process digital signals and images with practical applications in embedded systems. Developing micro-miniature processing units tailored for image processing and recognition in on-board mobile neural networks, known as Tiny ML or Edge AI, is of particular interest. These cutting-edge applications are at the forefront of modern technology.
For these reasons, the Tiny ML Summit has been held since 2019, bringing together experts from major companies and universities. The primary focus of this conference is to discuss the potential of transitioning machine learning from high-performance mainframes to small battery-powered signal microprocessors. The Tiny ML concept is continually evolving, driven by the development of dedicated chips designed for these applications. Notably, digital signal processing algorithms are pivotal in the systems under discussion. Over time, numerous algorithms and processor structures have been developed to address the challenges posed by these systems. With a focus on flexibility and versatility, the prevailing approach involves using universal signal microprocessors and FPGAs.
However, the high flexibility of the developed processors contradicts a highly efficient implementation. For example, a programmable signal processing unit is flexible, scalable and upgradable but highly inefficient in terms of performance, die area, weight, and power consumption.
Therefore, developing ASIC-centric solutions is best suited for portable applications as minimising power consumption, weight, and size of the processing unit in battery-powered systems has become an essential aspect of on-board processing.
At the algorithmic level, methods for reducing the above parameters usually focus on minimising the number of arithmetic operations, especially multiplications. In this regard, developing algorithms for performing the main filtering operations, characterised by minimal multiplicative complexity, is an urgent task. So, we again emphasise that convolution calculation is an essential mathematical macro operation in DNNs. And usually (though not always) it is computed using Winograd’s minimum filtering algorithm [1,12,14,18,20,21,22,40,41,42]. However, since, as already noted [43], this algorithm can only calculate two adjacent dot products, it is not suitable for all possible situations that can arise in neural networks. For example, Winograd’s minimum filtering algorithm is redundant for M = 3 and tile size (5 × 5) or for M = 5 and tile size (9 × 9). Many other examples could be given. In this article, we present algorithmic solutions for FIR filters with short-length impulse responses, which can be more efficient in some cases than Winograd’s minimal filtering algorithm.

3. Preliminary Remarks

The primary step in computing a 2D convolution involves taking the dot product between the vectors created by the sliding time window from the present data stream and the impulse response of an M-order finite impulse response (FIR) filter.
The procedure for computing convolution elements can be represented as follows in the most general case:
y j = i = 0 M 1 x i + j w i
j = 0 , 1 , , N M + 1 ,
where N represents the length of the current data stream, with { x i + j } denoting the elements of the data stream, and { w i } represents the constant coefficients of the FIR filter’s impulse response.
In a more detailed form, expression (1) can be represented as follows:
y 0 = w 0 x 0 + w 1 x 1 + + w M 1 x M 1 y 1 = w 0 x 1 + w 1 x 2 + + w M 1 x M y N M = w 0 x N M + w 1 x N M + 1 + + w M 1 x N 1
Figure 1 illustrates the sequence of steps in calculating the moving dot product.
The equations above comprehensively describe all the mathematical operations required for the calculations. However, strictly speaking, they do not constitute an algorithm since they do not reveal the specific sequence of calculations. In some instances, expressing the sliding dot product operation as a matrix-vector product is more convenient:
Y N M + 1 × 1 = W N M + 1 × N X N × 1
where:
Y N M + 1 × 1 = y 0 , y 1 , , y N M T ,
X N × 1 = x 0 , x 1 , , x N 1 T ,
W N M + 1 × N = w 0 w 1 w M 1 w 0 w 1 w M 1 w 0 w 1 w M 1 .
However, regarding the research task at hand, such a representation is unhelpful as it does not facilitate identifying opportunities for reducing the computational complexity of the procedure for determining the sliding inner product when the sequence is comprised of input signal samples.
Let us rewrite expressions (2) in the following form:
Y N M + 1 × 1 = X N M + 1 × M W M × 1
where:
W M × 1 = w 0 , w 1 , , w M 1 T ,
X N M + 1 × M = x 0 x 1 x M 1 x 1 x 2 x M x N M x N M + 1 x N 1 .
This form of writing is much more useful and legible, which will be visible in the next steps. It turns out that considering the structural properties of the matrix X N M + 1 × M in the expression (4) allows for a fairly significant reduction in the number of arithmetic operations. Let us consider this problem in more detail. Let us impose certain conditions on the sizes of the input sequences. Suppose N = M ( K + 1 ) 1 , where K = 1 , 2 , 3 , is a positive integer number. It is obvious that if the supposed requirement for N is not satisfied, sequences { x n } , n = 0 , 1 , , N 1 can be padded with zeros without losing computation precision.
Then the expression (4) takes the following form:
Y K M × 1 = X K M × M W M × 1
where:
Y K M × 1 = y 0 , y 1 , , y K M 1 T ,
X K M × M = X 1 × M 0 , X 1 × M 1 , , X 1 × M K M 1 T ,
and
X 1 × M i = x i , x i + 1 , , x M 1 + i , i = 0 , 1 , , K M 1 .
To see the structure of the matrix X K M × M , we present expression (5) in a more detailed form:
y 0 y 1 y K M 1 = x 0 x 1 x M 1 x 1 x 2 x M x M 1 x M x 2 M 2 x M x M + 1 x 2 M 1 x M + 1 x M + 2 x 2 M x 2 M 1 x 2 M x 3 M 2 x K 1 M x K 1 M + 1 x K M 1 x K 1 M + 1 x K 1 M + 2 x K M x K M 1 x K M x K 1 M 2 w 0 w 1 w M 1
By examining this description, it becomes evident that the matrix X K M × M possesses a block structure and comprises K submatrices of Hankel type. Thus, the calculation of the sliding dot product, taking into account the imposed conditions, comes down to multiplying the sequence of K sub-matrices (i.e. the Hankel matrices) by the vector W M × 1 and then combining the individual calculation results.
Hence, we establish the fundamental filtering operation in DNNs as multiplying the Hankel sub-matrix (formed from the current input data sequence using a sliding window of size M) by a vector whose elements are the impulse response coefficients of an M-order FIR filter. There are efficient algorithms for multiplying Hankel matrices by a vector. However, they are mainly focused on large matrices, the order of which is a power of two [44,45]. But in most cases of image processing in neural networks, the impulse responses of FIR filters are short and contain an odd number of coefficients. Under these conditions, we are dealing with Hankel matrices of small orders. When multiplying small-size Hankel matrices by small-length vectors, known algorithms are inefficient or even counterproductive. Therefore, we have developed our own algorithms explicitly focused on calculating matrix-vector products with Hankel matrices of small orders.
So, we define the basic filtering macrooperation as:
Y M × 1 = X M W M × 1
where:
X M = x 0 x 1 x M 1 x 1 x 2 x M x M 1 x M x 2 M 2 ,
Y M × 1 = y 0 ( M ) , y 1 ( M ) , , y M 1 ( M ) T ,
W M × 1 = w 0 ( M ) , w 1 ( M ) , , w M 1 ( M ) T .
(Kindly take note that from this point forward, the superscript M will signify quantities associated with the basic filtering macrooperation employing an M-order filter).
We emphasise once again that, as a rule, small-order filters are used in deep neural networks when the impulse response vectors contain a small number of elements. And almost always, we are dealing with an odd number of records. Based on the information provided above, this article aims to create and describe resource-efficient filtering algorithms for FIR filters with widely used orders: M = 3, 5, 7, and 9.

4. Minimal Filtering Algorithms

Let us show, based on specific examples, how it works.

4.1. Algorithm 1, M = 3

Let X 5 × 1 = x 0 , x 1 , x 2 , x 3 , x 4 T be a vector that represents the input data set, W 3 × 1 = w 0 ( 3 ) , w 1 ( 3 ) , w 2 ( 3 ) T be a vector that contains the coefficients of the impulse response of a 3-tap FIR filter, and Y 3 × 1 = y 0 ( 3 ) , y 1 ( 3 ) , y 2 ( 3 ) T be a vector describing the results of using a 3-tap FIR filter:
Y 3 × 1 = x 0 x 1 x 2 x 1 x 2 x 3 x 2 x 3 x 4 w 0 ( 3 ) w 1 ( 3 ) w 2 ( 3 )
As can be seen, calculating the product (8) requires 9 multiplications and 6 additions.
We can formulate a streamlined algorithm for computing Y 3 × 1 by utilising the following matrix-vector calculation procedure:
Y 3 × 1 = T 3 × 6 ( 3 ) D 6 ( 3 ) T 6 × 5 ( 3 ) X 5 × 1
where
T 3 × 6 ( 3 ) = 1 1 1 1 1 1 1 1 1 ,
T 6 × 5 ( 3 ) = 1 1 1 1 1 1 1 1 1 1 1 1 ,
and
D 6 ( 3 ) = d i a g s 0 ( 3 ) , s 1 ( 3 ) , , s 5 ( 3 ) ,
s 0 ( 3 ) , = w 0 ( 3 ) , s 1 ( 3 ) , = w 0 ( 3 ) + w 1 ( 3 ) , s 2 ( 3 ) , = w 1 ( 3 )
s 3 ( 3 ) = w 0 ( 3 ) + w 2 ( 3 ) , s 4 ( 3 ) = w 1 ( 3 ) + w 2 ( 3 ) , s 5 ( 3 ) = w 2 ( 3 ) .
Figure 2 depicts a data flow graph of the proposed algorithm for implementing the basic filtering operation for a 3-tap FIR filter. In this paper, the data flow diagrams are arranged from left to right, and straight lines in the figures represent data transfer operations. The circles in these figures indicate multiplication operations, with the corresponding numbers written inside the circles. The convergence points of the lines indicate summation, while dashed lines represent data transfer operations with a simultaneous change of sign. To maintain clarity, the figures utilise simple lines without arrows. Furthermore, to simplify the presentation, the superscripts of variables have been omitted in all figures, as the vector sizes involved in each case can be inferred from the figures themselves.

4.2. Algorithm 2, M = 5

Let X 9 × 1 = x 0 , x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 T be a vector that represents the input data set, W 5 × 1 = w 0 ( 5 ) , w 1 ( 5 ) , w 2 ( 5 ) , w 3 ( 5 ) , w 4 ( 5 ) T be a vector that contains the coefficients of the impulse response of a 5-tap FIR filter, and Y 5 × 1 = y 0 ( 5 ) , y 1 ( 5 ) , y 2 ( 5 ) , y 3 ( 5 ) , y 4 ( 5 ) T be a vector describing the results of using a 5-tap FIR filter:
Y 5 × 1 = x 0 x 1 x 2 x 3 x 4 x 1 x 2 x 3 x 4 x 5 x 2 x 3 x 4 x 5 x 6 x 3 x 4 x 5 x 6 x 7 x 4 x 5 x 6 x 7 x 8 w 0 ( 5 ) w 1 ( 5 ) w 2 ( 5 ) w 3 ( 5 ) w 4 ( 5 )
As can be seen, calculating the product (10) requires 25 multiplications and 20 additions.
We can devise a streamlined algorithm to compute Y 5 × 1 by employing the following matrix-vector calculation procedure:
Y 5 × 1 = T 5 × 14 ( 5 ) D 14 ( 5 ) T 14 × 9 ( 5 ) X 9 × 1
where
T 5 × 14 ( 5 ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
T 14 × 9 ( 5 ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
and
D 14 ( 5 ) = d i a g s 0 ( 5 ) , s 1 ( 5 ) , , s 13 ( 5 ) ,
s 0 ( 5 ) = w 0 ( 5 ) , s 1 ( 5 ) = w 0 ( 5 ) + w 1 ( 5 ) , s 2 ( 5 ) = w 0 ( 5 ) + w 2 ( 5 ) , s 3 ( 5 ) = w 0 ( 5 ) + w 1 ( 5 ) + w 2 ( 5 ) + w 3 ( 5 ) ,
s 4 ( 5 ) = w 1 ( 5 ) , s 5 ( 5 ) = w 0 ( 5 ) + w 4 ( 5 ) , s 6 ( 5 ) = w 1 ( 5 ) + w 3 ( 5 ) , s 7 ( 5 ) = w 2 ( 5 ) + w 3 ( 5 ) ,
s 8 ( 5 ) = w 2 ( 5 ) , s 9 ( 5 ) = w 1 ( 5 ) + w 4 ( 5 ) , s 10 ( 5 ) = w 3 ( 5 ) , s 11 ( 5 ) = w 2 ( 5 ) + w 4 ( 5 ) ,
s 12 ( 5 ) = w 3 ( 5 ) + w 4 ( 5 ) , s 13 ( 5 ) = w 4 ( 5 ) .
Figure 3 illustrates a data flow graph of the proposed algorithm for implementing the basic filtering operation for a 5-tap FIR filter.

4.3. Algorithm 3, M = 7

Let X 13 × 1 = x 0 , x 1 , , x 12 T be a vector that represents the input data set, W 7 × 1 = w 0 ( 7 ) , w 1 ( 7 ) , , w 6 ( 7 ) T be a vector that contains the coefficients of the impulse response of a 7-tap FIR filter, and Y 7 × 1 = y 0 ( 7 ) , y 1 ( 7 ) , , y 6 ( 7 ) T be a vector describing the results of using a 7-tap FIR filter:
Y 7 × 1 = x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 6 x 7 x 8 x 9 x 10 x 11 x 12 w 0 ( 7 ) w 1 ( 7 ) w 2 ( 7 ) w 3 ( 7 ) w 4 ( 7 ) w 5 ( 7 ) w 6 ( 7 )
As can be seen, calculating the product (12) requires 49 multiplications and 42 additions.
We can formulate a streamlined algorithm for computing Y 7 × 1 by utilising the following matrix-vector calculation procedure:
Y 7 × 1 = T 7 × 15 ( 7 ) T 15 × 25 ( 7 ) D 25 ( 7 ) T 25 × 18 ( 7 ) T 18 × 13 ( 7 ) X 13 × 1
where
T 7 × 15 ( 7 ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
T 9 × 18 ( 7 ) = T 3 × 6 ( 3 ) 0 3 × 6 0 3 × 6 0 3 × 6 T 3 × 6 ( 3 ) 0 3 × 6 0 3 × 6 0 3 × 6 T 3 × 6 ( 3 ) , T 9 × 7 ( 7 ) = 1 0 1 × 6 0 8 × 1 0 8 × 6 ,
T 6 × 7 ( 7 ) = 1 1 1 1 1 1 1 1 1 1 1 1 , T 15 × 25 ( 7 ) = T 9 × 18 ( 7 ) T 9 × 7 ( 7 ) 0 6 × 18 T 6 × 7 ( 7 ) ,
T 6 × 8 ( 7 ) = T 6 × 5 ( 3 ) 0 6 × 3 , T ˜ 6 × 8 ( 7 ) = 0 6 × 3 T 6 × 5 ( 3 ) , T 12 × 8 ( 7 ) = T 6 × 8 ( 7 ) T ˜ 6 × 8 ( 7 ) ,
T 10 × 5 ( 7 ) = 1 1 1 1 1 , T 10 ( 7 ) = 0 10 × 4 T 10 × 5 ( 7 ) 0 10 × 1 ,
T 12 × 10 ( 7 ) = 0 2 × 10 T 10 ( 7 ) , T 6 × 10 ( 7 ) = T 6 × 5 ( 3 ) 0 6 × 5 , T 6 × 7 ( 7 ) = I 6 0 6 × 1 ,
T 1 × 7 ( 7 ) = 1 1 1 1 1 1 1 ,
T 7 ( 7 ) = T 6 × 7 ( 7 ) T 1 × 7 ( 7 ) , T 7 × 10 ( 7 ) = 0 7 × 3 T 7 ( 7 ) , T 13 × 10 ( 7 ) = T 6 × 10 ( 7 ) T 7 × 10 ( 7 ) ,
T 25 × 18 = T 12 × 8 ( 7 ) T 12 × 10 0 13 × 8 T 13 × 10 ,
T 8 × 11 ( 7 ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
T 8 × 13 ( 7 ) = T 8 × 11 ( 7 ) 0 8 × 2 , T 10 × 13 ( 7 ) = 0 10 × 3 I 10 , T 18 × 13 = T 8 × 13 ( 7 ) T 10 × 13 ( 7 ) ,
and
D 25 ( 7 ) = d i a g s 0 ( 7 ) , s 1 ( 7 ) , , s 24 ( 7 ) ,
s 0 ( 7 ) = w 0 ( 7 ) , s 1 ( 7 ) = w 0 ( 7 ) + w 1 ( 7 ) , s 2 ( 7 ) = w 1 ( 7 ) , s 3 ( 7 ) = w 0 ( 7 ) + w 2 ( 7 ) , s 4 ( 7 ) = w 1 ( 7 ) + w 2 ( 7 ) ,
s 5 ( 7 ) = w 2 ( 7 ) , s 6 ( 7 ) = w 3 ( 7 ) , s 7 ( 7 ) = w 3 ( 7 ) + w 4 ( 7 ) , s 8 ( 7 ) = w 4 ( 7 ) , s 9 ( 7 ) = w 3 ( 7 ) + w 5 ( 7 ) ,
s 10 ( 7 ) = w 4 ( 7 ) + w 5 ( 7 ) , s 11 ( 7 ) = w 5 ( 7 ) , s 12 ( 7 ) = w 3 ( 7 ) w 0 ( 7 ) , s 13 ( 7 ) = w 3 ( 7 ) + w 4 ( 7 ) w 0 ( 7 ) w 1 ( 7 ) ,
s 14 ( 7 ) = w 4 ( 7 ) w 1 ( 7 ) , s 15 ( 7 ) = w 3 ( 7 ) + w 5 ( 7 ) w 0 ( 7 ) w 2 ( 7 ) , s 16 ( 7 ) = w 4 ( 7 ) + w 5 ( 7 ) w 1 ( 7 ) w 2 ( 7 ) ,
s 17 ( 7 ) = w 5 ( 7 ) w 2 ( 7 ) , s 18 ( 7 ) = w 0 ( 7 ) + w 6 ( 7 ) , s 19 ( 7 ) = w 1 ( 7 ) + w 6 ( 7 ) , s 20 ( 7 ) = w 2 ( 7 ) + w 6 ( 7 ) ,
s 21 ( 7 ) = w 3 ( 7 ) + w 6 ( 7 ) , s 22 ( 7 ) = w 4 ( 7 ) + w 6 ( 7 ) , s 23 ( 7 ) = w 5 ( 7 ) + w 6 ( 7 ) , s 24 ( 7 ) = w 6 ( 7 ) .
Figure 4 illustrates a data flow graph of the proposed algorithm for implementing the basic filtering operation for a 7-tap FIR filter.

4.4. Algorithm 4, M = 9

Let X 17 × 1 = x 0 , x 1 , , x 16 T be a vector that represents the input data set, W 9 × 1 = w 0 ( 9 ) , w 1 ( 9 ) , , w 8 ( 9 ) T be a vector that contains the coefficients of the impulse response of a 9-tap FIR filter, and Y 9 × 1 = y 0 ( 9 ) , y 1 ( 9 ) , , y 8 ( 9 ) T be a vector describing the results of using a 9-tap FIR filter:
Y 9 × 1 = x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 w 0 ( 9 ) w 1 ( 9 ) w 2 ( 9 ) w 3 ( 9 ) w 4 ( 9 ) w 5 ( 9 ) w 6 ( 9 ) w 7 ( 9 ) w 8 ( 9 )
As can be seen, calculating the product (14) requires 81 multiplications and 72 additions.
We can formulate a streamlined algorithm for computing Y 9 × 1 by utilising the following matrix-vector calculation procedure:
Y 9 × 1 = T 9 × 18 ( 9 ) T 18 × 36 ( 9 ) D 36 ( 9 ) T 36 × 30 ( 9 ) T 30 × 17 ( 9 ) X 17 × 1
where
T 9 × 18 ( 9 ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
T ˜ 9 × 18 ( 9 ) = T 3 × 6 ( 3 ) 0 3 × 6 0 3 × 6 0 3 × 6 T 3 × 6 ( 3 ) 0 3 × 6 0 3 × 6 0 3 × 6 T 3 × 6 ( 3 ) , T 18 × 36 ( 9 ) = T ˜ 9 × 18 ( 9 ) 0 9 × 18 0 9 × 18 T ˜ 9 × 18 ( 9 ) ,
T 6 × 10 ( 9 ) = T 6 × 5 ( 3 ) 0 6 × 5 , T ˜ 6 × 10 ( 9 ) = 0 6 × 5 T 6 × 5 ( 3 ) , T 12 × 10 ( 9 ) = T 6 × 10 ( 9 ) T ˜ 6 × 10 ( 9 ) ,
T 36 × 30 ( 9 ) = T 12 × 10 ( 9 ) 0 12 × 10 0 12 × 10 0 12 × 10 T 12 × 10 ( 9 ) 0 12 × 10 0 12 × 10 0 12 × 10 T 12 × 10 ( 9 ) ,
T 5 × 11 ( 9 a ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
T 5 × 11 ( 9 b ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
T 5 × 11 ( 9 c ) = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,
T 5 × 17 ( 9 a ) = T 5 × 11 ( 9 a ) 0 5 × 6 , T 5 × 17 ( 9 b ) = 0 5 × 3 I 5 0 5 × 9 ,
T 5 × 17 ( 9 c ) = 0 5 × 3 T 5 × 11 ( 9 b ) 0 5 × 3 , T 5 × 17 ( 9 d ) = 0 5 × 6 I 5 0 5 × 6 ,
T 5 × 17 ( 9 e ) = 0 5 × 9 I 5 0 5 × 3 , T 5 × 17 ( 9 f ) = 0 5 × 6 T 5 × 11 ( 9 c ) ,
T 30 × 17 ( 9 ) = T 5 × 17 ( 9 a ) T 5 × 17 ( 9 b ) T 5 × 17 ( 9 c ) T 5 × 17 ( 9 d ) T 5 × 17 ( 9 e ) T 5 × 17 ( 9 f ) ,
D 36 ( 9 ) = d i a g s 0 ( 9 ) , s 1 ( 9 ) , , s 35 ( 9 ) ,
s 0 ( 9 ) = w 0 ( 9 ) , s 1 ( 9 ) = w 0 ( 9 ) + w 1 ( 9 ) , s 2 ( 9 ) = w 1 ( 9 ) , s 3 ( 9 ) = w 0 ( 9 ) + w 2 ( 9 ) , s 4 ( 9 ) = w 1 ( 9 ) + w 2 ( 9 ) ,
s 5 ( 9 ) = w 2 ( 9 ) , s 6 ( 9 ) = w 0 ( 9 ) + w 3 ( 9 ) , s 7 ( 9 ) = w 0 ( 9 ) + w 1 ( 9 ) + w 3 ( 9 ) + w 4 ( 9 ) , s 8 ( 9 ) = w 1 ( 9 ) + w 4 ( 9 ) ,
s 9 ( 9 ) = w 0 ( 9 ) + w 2 ( 9 ) + w 3 ( 9 ) + w 5 ( 9 ) , s 10 ( 9 ) = w 1 ( 9 ) + w 2 ( 9 ) + w 4 ( 9 ) + w 5 ( 9 ) , s 11 ( 9 ) = w 2 ( 9 ) + w 5 ( 9 ) ,
s 12 ( 9 ) = w 3 ( 9 ) , s 13 ( 9 ) = w 3 ( 9 ) + w 4 ( 9 ) , s 14 ( 9 ) = w 4 ( 9 ) , s 15 ( 9 ) = w 3 ( 9 ) + w 5 ( 9 ) , s 16 ( 9 ) = w 4 ( 9 ) + w 5 ( 9 ) ,
s 17 ( 9 ) = w 5 ( 9 ) , s 18 ( 9 ) = w 0 ( 9 ) + w 6 ( 9 ) , s 19 ( 9 ) = w 0 ( 9 ) + w 1 ( 9 ) + w 6 ( 9 ) + w 7 ( 9 ) , s 20 ( 9 ) = w 1 ( 9 ) + w 7 ( 9 ) ,
s 21 ( 9 ) = w 0 ( 9 ) + w 2 ( 9 ) + w 6 ( 9 ) + w 8 ( 9 ) , s 22 ( 9 ) = w 1 ( 9 ) + w 2 ( 9 ) + w 7 ( 9 ) + w 8 ( 9 ) , s 23 ( 9 ) = w 2 ( 9 ) + w 8 ( 9 ) ,
s 24 ( 9 ) = w 3 ( 9 ) + w 6 ( 9 ) , s 25 ( 9 ) = w 3 ( 9 ) + w 4 ( 9 ) + w 6 ( 9 ) + w 7 ( 9 ) , s 26 ( 9 ) = w 4 ( 9 ) + w 7 ( 9 ) ,
s 27 ( 9 ) = w 3 ( 9 ) + w 5 ( 9 ) + w 6 ( 9 ) + w 8 ( 9 ) , s 28 ( 9 ) = w 4 ( 9 ) + w 5 ( 9 ) + w 7 ( 9 ) + w 8 ( 9 ) , s 29 ( 9 ) = w 5 ( 9 ) + w 8 ( 9 ) ,
s 30 ( 9 ) = w 6 ( 9 ) , s 31 ( 9 ) = w 6 ( 9 ) + w 7 ( 9 ) , s 32 ( 9 ) = w 7 ( 9 ) , s 33 ( 9 ) = w 6 ( 9 ) + w 8 ( 9 ) , s 34 ( 9 ) = w 7 ( 9 ) + w 8 ( 9 ) ,
s 35 ( 9 ) = w 8 ( 9 ) .
Figure 5 illustrates a data flow graph of the proposed algorithm for implementing the basic filtering operation for a 9-tap FIR filter.

5. Implementation Complexity

Due to the relatively small lengths of the input sequences and the straightforward nature of the data flow diagrams depicting the computation process, it is easy to assess the implementation complexity of the proposed solutions. Table 1 estimates the number of arithmetic blocks required for the fully parallel implementation of the filtering algorithms designed for short lengths. The values presented in the table can be regarded as an approximate measure of the implementation cost on an ASIC.
As we can see, using the proposed algorithmic solutions to construct digital filtering cores results in fewer multipliers being needed than using naive approaches to their design. In the context of designing specialised fully parallel VLSI processors, minimising the number of multipliers is of paramount importance. This approach significantly reduces the cost of implementing the entire system and mitigates power dissipation. This is due to the hardware multiplier’s higher level of complexity and larger chip area occupation than the adder. It has been demonstrated that the hardware cost of a binary adder rises linearly with the operand size. In contrast, the implementation cost of a hardwired multiplier escalates quadratically with the operand size [46]. Hence, reducing the number of multipliers, even if it results in a slight increase in the number of adders, significantly influences the hardware implementation of digital filtering cores.
The proposed algorithms have been exemplarily implemented in FPGAs on the simplest possible devices of Xilinx’s Spartan 3 series. The criterion for selecting a model from the Spartan 3 family was to provide a sufficient number of inputs and outputs. The 8-bit inputs X ( 2 M 1 ) × 1 , 16-bit outputs Y 9 × 1 , and fixed 8-bit coefficients of the impulse response of the FIR filter W M × 1 , were assumed. Table 2 shows the number of slices used in the Spartan 3 FPGA implementation. The number of uses multipliers MULT 18 × 18 is also shown in this table, but both algorithms mostly used all hardware-accessible multipliers. Only for size M = 5 was the number of available multipliers is for the proposed algorithm greater than required, and only in this case did the algorithm not use all of them. Table 3 shows the number of four input LUTs used in the Spartan 3 FPGA implementation. For each size M, the proposed algorithms achieved a reduction of the logic blocks used. The smallest was for the size M = 3 , where the reduction was only about 1% for the slices and 2,4% for four inputs LUTs. The biggest was for size M = 5 , which achieves nearly a 40% decrease in logical blocks.

6. Conclusions

This study explores methods to reduce the multiplicative complexity of conducting basic filtering operations for M-tap FIR filters with short impulse responses, commonly used in convolutional neural networks. Additionally, new algorithms for resource-efficient implementations of these algorithms have been devised for M values of 3, 5, 7, and 9. By utilising these algorithms, basic filtering operations computational complexity is reduced, which also lessens the difficulty of their hardware implementation. Reducing the number of multiplications in the algorithms comes at the expense of some increase in the number of additions. However, this is not significant due to the much higher implementation cost of the hardware multiplier relative to the adder. Some limitation of the proposed algorithms is the increased complexity of data manipulation. For this reason, it seems particularly advantageous to implement the proposed solutions in ASICs. The distinctive feature of all the proposed algorithms is their evident parallel and modular structures. The modularity allows unifying the implementation of the algorithms in FPGAs and makes it easier to map them into ASIC structures. Consequently, the parallelisation of computing processes enables accelerated computations during the execution of these algorithms. The implementation of the proposed algorithms in DNNs will be a target for further research.

Author Contributions

Conceptualization, A.C.; methodology, A.C., J.P.P. and M.M.; formal analysis, A.C., J.P.P. and M.M.; writing—original draft preparation, A.C.; writing—review and editing, A.C. and J.P.P.; visualization, A.C., M.M. and J.P.P.; supervision, A.C. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Conflicts of Interest

The authors declare no conflict of interest.

Abbreviations

The following abbreviations are used in this manuscript:
VLSIvery large-scale integration
DNNdeep neural networks
FFTfast Fourier transform
FIRfinite impuls responce
FPGAfield programmable gate array
GPUgraphics processing unit
ASICapplication-specific integrated circuit
Tiny MLTiny machine learning
Edge AIEdge artificial intelligence
MULTMultiplication
LUTlook up table

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Figure 1. The illustration of the step sequences during calculating the moving dot product.
Figure 1. The illustration of the step sequences during calculating the moving dot product.
Applsci 13 09004 g001
Figure 2. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 3.
Figure 2. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 3.
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Figure 3. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 5.
Figure 3. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 5.
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Figure 4. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 7.
Figure 4. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 7.
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Figure 5. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 9.
Figure 5. Data flow graph of the algorithm for implementing the basic filtering operation for the case M = 9.
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Table 1. The complexities of implementing of the naive and proposed solutions.
Table 1. The complexities of implementing of the naive and proposed solutions.
Size MNumbers of Arithmetic Blocks
Naive MethodProposed Algorithm
MultipliersM-Input
Adders
Multipliers2-Input
Adders
3-Input
Adders
4-Input
Adders
M -Input
Adders
3936-6--
5255144--10
74972572411
981936-60--
Table 2. The number of the multipliers MULT 18 × 18, and the slices used in the Spartan 3 FPGA implementations.
Table 2. The number of the multipliers MULT 18 × 18, and the slices used in the Spartan 3 FPGA implementations.
MULT 18 × 18Slices
Size MDevicesSchoolProposedSchoolProposedReduction
3xc3s50-4pq208441111100.9%
5xc3s400-4fg456161456334239.3%
7xc3s400-4fg456161677668411.9%
9xc3s1000-4fg67624241303106618.2%
Table 3. The number of the 4 input LUTs used in the Spartan 3 FPGA implementations.
Table 3. The number of the 4 input LUTs used in the Spartan 3 FPGA implementations.
4 Input LUTs
Size MDevicesSchoolProposedReduction
3xc3s50-4pq2082072022.4%
5xc3s400-4fg456104063638.8%
7xc3s400-4fg4561441128410.9%
9xc3s1000-4fg6762456199418.8%
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Cariow, A.; Papliński, J.P.; Makowska, M. VLSI-Friendly Filtering Algorithms for Deep Neural Networks. Appl. Sci. 2023, 13, 9004. https://doi.org/10.3390/app13159004

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Cariow A, Papliński JP, Makowska M. VLSI-Friendly Filtering Algorithms for Deep Neural Networks. Applied Sciences. 2023; 13(15):9004. https://doi.org/10.3390/app13159004

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Cariow, Aleksandr, Janusz P. Papliński, and Marta Makowska. 2023. "VLSI-Friendly Filtering Algorithms for Deep Neural Networks" Applied Sciences 13, no. 15: 9004. https://doi.org/10.3390/app13159004

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