A Power-Efficient High-Drive Current Mirror Combining a Regulated Cascode Topology with a Non-Linear CCII-Based Feedback

Round 1

Reviewer 1 Report

The paper is about a high-speed current mirror with high current handling capacity using two feedback loops, however, some points have to be clarified before thinking about it being publishable, among others:

1. The paper is a slight variation of the reference [8] so its contribution is marginal.

2. It lacks mathematical rigor which is a serious deficiency.

3. A current mirror has several important parameters that measure its performance, among others:

(a) Minimum turn-on voltage

(b) High output impedance.

(c) Low input impedance.

(d) Linearity.

(e). Have a large bandwidth in Io/Iin transfer function.

etc.

Since the article claims that the current mirror is high-speed, it must have a large bandwidth, so some of the above parameters must be given as a function of frequency, especially input impedance, output impedance and the Io/Iin transfer function.

Thus, the fundamental point is to carry out the mathematical analysis of the proposed circuit, identify the important parameters that can be adjusted, and carry out a simulation that corroborates the predictions of the equations.

4. In this sense, an important point is Table 4 where the results obtained are compared. The following observations must be taken into account:

(a) The comparison of this Table is not fair since, for example, Reference 10 corresponds to a 500nm technology. They must be compared with references that use the same technology. Furthermore, the results of Reference [10] are silicon-proven not just simulations.

(b) Reference [10] does not give the efficiency data, how was it concluded that it is 70%?

(c) The mathematical equation for “Bandwidth” must be calculated and compared with your simulations.

(d) How the "Power Efficiency" was obtained (i.e. comment/shows your testbench.)

(e) Table 4 should be changed to one where the comparison is fairer (same technology, only simulations or only silicon-proven, etc.) and with more recent works (reference [10] date is 2012, reference [11] is 2002).

Additionally, input-swing, output-swing, static power silicon area, technology, minimum operating voltage and THD must be added to the table. Also, to be convincing, (or for clarity), you must include a row with the mathematical expressions for BW and power efficiency and compare them with similar parameter values.

5. Since the NL-CCII is the important block in the performance of the entire circuit, a complete characterization of it must be given (input impedance at node X, voltage copy error at node Y, current copy errors at node Z, etc.)

6. Regarding Figure 1.

For figure 1 (and all other figures from 1-5) it should be clearly indicated where there are contact points and where there are not (use “solder-dots”!).

(a) The equation describing the output current must be given.

(b) What are the mathematical expressions for Cin and Rin depending on the parameters of the transistors?

(c) Why i=0?

(d) What does mean "cste"?

(e) What does the trapezoid symbol mean? Is it an OTA? Does it represent the output transistor? Include a more detailed explanation of this figure.

7. Regarding Figure 2:

(a) Since the Z output of a CCII is current (high impedance) the loop of M20 is open. How is the loop closed?

(b) The output Z of a CCII is current. How is a current feedback to the gate of a transistor?

8 Regarding Figure 4:

(a) Give details of the operating point.

(b) A detailed description of the CCII shall be given in a separate section.

(c) How good is the voltage copy from the CII (node Y to node X)? How good is the CCII current copy (node X to node Z)?

(e) What is the mathematical expression for input impedance as a function of frequency (node X).

(f) Who controls the voltage at nodes B0-B7?

(g) What effect do these voltages have on your results?

9. Table 1. Missing spaces between ME, MF, MI in the figure caption of Table 1.

10. Regarding Figure 6:

(a) The mathematical expressions of each curve should be given and compared with the simulation results.

11. Regarding Table 2.

(a) Define what tr0.4% is .

12. Section 3.2. You cannot talk about "measurements" they are only simulations.

13. Table 3:

(a) The "bias" param is increasing, except in the last one.  Is that correct?.

14. Line 178:

(a) What is the parameter "t" and what is the parameter "r"?

15. Regarding Figure 7:

The mathematical equation for the "DC error copy" must be given and compared with simulations.

16. Regarding Figure 8:

(a) What was the testbench for each of the graphs in Figure 8?

(b) What does "stimuli cases" in the bottom of figure 8 mean?

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 2 Report

This paper presents a continuously regulated current mirror topology capable to provide wide range of currents with high-precision and speed control features. However, the novelty is very limited compared to previous works, especially [8]. The presented design is straightforward.

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

I would like to thank the authors for their effort in responding to the comments made on their paper, however, it is disappointing that they have left some of them unanswered and have only tried to answer them in a general way.

Although some of my comments have already been answered in the latest version of the paper, you must prepare a response by answering my previous comments on a point-to-point basis. In the end, I am rewriting my previous comments so that a response will be prepared for each of them.

 COMMENTS REGARDING THE LATEST VERSION OF THE ARTICLE.

1. According to your results, the proposed current mirror is not high speed, since the output node is of high impedance and the capacitances connected to this node (including parasitic ones) will reduce the speed drastically. This is corroborated in Figure 10 and Table 5, where the proposed circuit has the worst bandwidth. The above comment should be considered in the title of the paper.

2. Lines 53-54: The statement: "Consequently, no voltage variation across the equivalent input impedance (CIN//RIN) results in negligible current flow through it" is not entirely true because a very low impedance can have very low voltage change but very noticeable current.

3. Figure 3: There is a positive feedback path (OPAMP, M23, M21, M20) that must be carefully designed to prevent oscillation. What are the design considerations to prevent the circuit from oscillating?

4. Figure 4: The terminal Z in a CCII provides an output current, so, it is not clear how this current is injected to the gate of the transistor. You must elaborate more on this.

5. Figure 5: The meaning of the block whose input is IG and its output is VG is not clear. Describe this block in detail.

6. Section 2.2 System Model: Now your paper is more confusing, many variables need to be defined. Expressions must be given for each of the time constants, beta, gZ, gin(VD), wCC, wCM, etc., all of them in terms of the MOS transistor small signal parameters (i.e., gm, ro, cgs, cgd, etc).

7. Equation (5): Equation (5) is an improper fraction. According to equation (6), tau_1 < tau_2, therefore the pole of equation (5) occurs first, then the zero. The above indicates that the magnitude of the transfer function grows indefinitely with frequency, which is incorrect. Something is wrong.

 8. Lines 190-191: In Figure 7 there are no Wilson current mirrors.

9. Table 5. THD comparison is not clear, because if your input amplitude is very small, THD is almost zero. On the other hand, if your input amplitude is close to VDD (or close Ibias for input currents) your THD is large. In conclusion, THD must indicate the input amplitude as a percentage of VDD (or a percentage of Ibias in the case of current). It is expected that your THD be worse due to the non-linear behavior of the CCII.

 10. Point 6.1 (previous comments) The recommendations of point 6.1 were ignored in Figures 1, 2, 3, 4, 7, and 8.

11. Typos:

-In the author's section: [email protected]

Line 305: structure structure.

PREVIOUS COMMENTS: PLEASE RESPOND TO EACH OF THEM IN A POINT-BY-POINT BASIS.

1. The article is a slight variation of the reference [8] so its contribution is marginal.

2. It lacks mathematical rigor which is a serious deficiency.

3. A current mirror has several important parameters that measure its performance, among others:

(a) Minimum ignition voltage

(b) The output impedance.

(c) The input impedance.

(d) Linearity.

(and). Have a large bandwidth in Io/Iin transfer function.

Since the article mentions that the current mirror is high speed, it must have large bandwidth, so some of the above parameters must be given as a function of frequency, especially input impedance, output impedance and the Io/Iin transfer function.

Thus, the fundamental point is to carry out the mathematical analysis of the proposed circuit, identify the important parameters that can be adjusted and carry out a simulation that corroborates the predictions of the equations.

4. In this sense, an important point is Table 4 where the results obtained are compared. The following observations must be taken into account:

(a) The comparison of this Table is not fair since, for example, reference 10 corresponds to a 500nm technology. They must be compared with references that use the same technology. Furthermore, the results of Ref10 are silicon-proven not just simulations.

(b) Reference [10] does not give the efficiency data, where was it concluded that it is 70%?

(c) The mathematical equation for “Bandwidth” must be given and compared with your simulations.

(d) How the "Power Efficiency" was obtained (i.e. shows your testbench.)

(e) Table 4 should be changed to one where the comparison is fairer (same technology, only simulations or only silicon-proven) and which are more recent works (reference [10] is from 2012, reference [11] is 2002).

Additionally, input-swing, output-swing, static power silicon area, technology, minimum operating voltage and THD must be added to the table.

To be convincing, (or for clarity), you must include a row with the mathematical expressions for BW and power efficiency and compare them with similar parameter values.

5. Since the NL-CCII is the important block in the performance of the entire circuit, a complete characterization of it must be given (input impedance at node X, voltage copy error at node Y, current copy errors at node Z)

6. Regarding Figure 1.

For figure 1 (and all other figures from 1-5) it should be clearly indicated where there are contact points and where there are not (use “solder dots”!).

(a) The equation describing the output current must be given.

(b) What is Cin and Rin depending on the parameters of the transistors?

(c) Why i=0?

(d) What is this?

(e) What does the trapezoid symbol mean? Is it an OTA? Does it represent the output transistor? Prepare a more detailed explanation of this figure.

7.Regarding Figure 2:

(a) Since the Z output of a CCII is current (high impedance) the loop of M20 is open. How is the loop closed?

(b) The output Z of a CCII is current. How is a current fed back to the gate of a transistor?

8 Regarding Figure 4:

(a) Give details of the operating point.

(b) A detailed description of the CCII shall be given in a separate section.

(c) How good is the voltage copy from the CII (node Y to node X)? How good is the CCII current copy (node X to node Z)?

(e) What is the mathematical expression for input impedance as a function of frequency (node

(f) Who controls the voltage at nodes B0-B7?

(g) What effect do these voltages have on your results?

9. Table 1. Missing spaces between ME, MF, MI in the figure caption of Table 1.

10. Regarding Figure 6:

(a) The mathematical expressions of each curve should be given and compared with the simulation results.

11. Regarding Table 2.

(a) Define what tr0.4% is

12. Section 3.2. You cannot talk about "measurements" they are only simulations.

13. Table 3:

(a) The bias param is increasing, except In the last value, The paper is about a high-speed current mirror with high current handling capacity using two feedback loops, however, some points have to be clarified before thinking about it being publishable, among others:

1. The paper is a slight variation of the reference [8] so its contribution is marginal.

2. It lacks mathematical rigor which is a serious deficiency.

3. A current mirror has several important parameters that measure its performance, among others:

(a) Minimum turn-on voltage

(b) High output impedance.

(c) Low input impedance.

(d) Linearity.

(e). Have a large bandwidth in Io/Iin transfer function.

etc.

Since the article claims that the current mirror is high-speed, it must have a large bandwidth, so some of the above parameters must be given as a function of frequency, especially input impedance, output impedance and the Io/Iin transfer function.

Thus, the fundamental point is to carry out the mathematical analysis of the proposed circuit, identify the important parameters that can be adjusted, and carry out a simulation that corroborates the predictions of the equations.

4. In this sense, an important point is Table 4 where the results obtained are compared. The following observations must be taken into account:

(a) The comparison of this Table is not fair since, for example, Reference 10 corresponds to a 500nm technology. They must be compared with references that use the same technology. Furthermore, the results of Reference [10] are silicon-proven not just simulations.

(b) Reference [10] does not give the efficiency data, how was it concluded that it is 70%?

(c) The mathematical equation for “Bandwidth” must be calculated and compared with your simulations.

(d) How the "Power Efficiency" was obtained (i.e. comment/shows your testbench.)

(e) Table 4 should be changed to one where the comparison is fairer (same technology, only simulations or only silicon-proven, etc) and with more recent works (reference [10] date is 2012, reference [11] is 2002).

Additionally, input-swing, output-swing, static power silicon area, technology, minimum operating voltage and THD must be added to the table. Also, to be convincing, (or for clarity), you must include a row with the mathematical expressions for BW and power efficiency and compare them with similar parameter values.

5. Since the NL-CCII is the important block in the performance of the entire circuit, a complete characterization of it must be given (input impedance at node X, voltage copy error at node Y, current copy errors at node Z, etc.)

6. Regarding Figure 1.

For figure 1 (and all other figures from 1-5) it should be clearly indicated where there are contact points and where there are not (use “solder-dots”!).

(a) The equation describing the output current must be given.

(b) What are the mathematical expression for Cin and Rin depending on the parameters of the transistors?

(c) Why i=0?

(d) What does mean "cste"?

(e) What does the trapezoid symbol mean? Is it an OTA? Does it represent the output transistor? Include a more detailed explanation of this figure.

7. Regarding Figure 2:

(a) Since the Z output of a CCII is current (high impedance) the loop of M20 is open. How is the loop closed?

(b) The output Z of a CCII is current. How is a current feedback to the gate of a transistor?

8 Regarding Figure 4:

(a) Give details of the operating point.

(b) A detailed description of the CCII shall be given in a separate section.

(c) How good is the voltage copy from the CII (node Y to node X)? How good is the CCII current copy (node X to node Z)?

(e) What is the mathematical expression for input impedance as a function of frequency (node X).

(f) Who controls the voltage at nodes B0-B7?

(g) What effect do these voltages have on your results?

9. Table 1. Missing spaces between ME, MF, MI in the figure caption of Table 1.

10. Regarding Figure 6:

(a) The mathematical expressions of each curve should be given and compared with the simulation results.

11. Regarding Table 2.

(a) Define what tr0.4% is .

12. Section 3.2. You cannot talk about "measurements" they are only simulations.

13. Table 3:

(a) The "bias" param is increasing, except in the last one.  Is that correct?.

14. Line 178:

(a) What is the parameter "t" and what is the parameter "r"?

15. Regarding Figure 7:

The mathematical equation for the "DC error copy" must be given and compared with simulations.

16. Regarding Figure 8:

(a) What was the testbench for each of the graphs in Figure 8?

(b) What does "stimuli cases" in the bottom of figure 8 mean?

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

The paper can be accepted.

Author Response

Dear Reviewer,

Thank you very much for approving my manuscript for publication. Your feedback was incredibly helpful and made my paper much better. I really appreciate the time and effort you put into reviewing my work.

Thanks again for everything. I'm looking forward to seeing my research published and hope it contributes well to our field.

Best regards.

Round 3

Reviewer 1 Report

I want to express my gratitude to the authors for their effort in considering my comments on their manuscript. The intention is just to improve the paper.

A couple of final comments follow:

Figure 7. Missing solder points between the Z output and the cascode transistors.

Comment to "Comment 4. Figure 4". I think there is a misinterpretation of the author's concept of integrating the CCII output current using the capacitor of M20 and M21, for the following reasons:

-The capacitance of a MOS is of the order of femto Farads, obviously its value depends on W and L.

-In case the current is integrated through the gate capacitor, the voltage generated is:

VG=I*t/CGS = I*t*1E13 (if we consider a typical capacitor value of 100fF)

If we consider a typical current value I=1nano Amp (lower values are already close to the channel noise) and since the circuit operates in continuous time, in just 1 second we will have, VG=10^4 Volts, which it is not possible. If the current is integrated continuously, the value of VG is larger.

-For the ideal case that CCII has a very large (infinite) resistance, it is not possible to have an operating point for transistors M20 and M21, and therefore VG remains undefined.

-Your circuit may be working perhaps because in a closed loop the CCII behaves like an OPAMP.

-Additionally, all the output capacitances of the Z terminal (cascode transistors) contribute to forming a greater capacitance in the Z node.

-The output resistance of the CCII (cascodes) decreased by the feedback factor helps define the operating point.

The previous points maybe could explain the operation of the proposed circuit, but not the arguments given in response by the authors.

Author Response

Please see the attachment

Author Response File: Author Response.pdf