High-Speed CNN Accelerator SoC Design Based on a Flexible Diagonal Cyclic Array
, Sang-Bo Park 1, Hyung-Won Kim 1, Keon-Myung Lee 2 and Sang-Hoon Sim 1,*
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe paper is well structured and the main contribution is scientific described. The paper needs only English editor for formal phrases.
However, in Fig. 14 the Authors describe very litle the implementation on 14um technology of the SoC. There is no further explainations that sustain such need for a ASIC implementation.
Author Response
Dear Reviewer 1
Based on the review, we have provided additional details regarding the area specifications at line [527]. Should there be any further requirements concerning the implementation, please don't hesitate to specify. Thank you.
Reviewer 2 Report
Comments and Suggestions for AuthorsComments for author File: 
Comments.pdf
English language improvement is required, there are some capitalization and abbreviation problems.
Author Response
Dear Reviewer 2
1.
We have corrected the capital letter and abbreviation problems throughout the paper. The revisions are listed below.
Line [12]: Convolution Neural Network (CNN).
Line [19]: Processing Element (PE)
Line [20]: YOLOv5.
Line [69]: Flexible Diagonal Cyclic Array (FDCA).
Line [151]: Systolic Array (SA).
From line [214]: Kernel Unit (KU).
Line [402]: Batch Normalization (BN).
2.
We have checked that some of graphics have poor quality.
We replaced Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 11 including the figure you mentioned.
