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Article

SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect

by
Ling Sang
1,2,
Rui Jin
1,2,*,
Jiawei Cui
3,
Xiping Niu
1,2,
Zheyang Li
1,2,
Junjie Yang
3,
Muqin Nuo
3,
Meng Zhang
4,
Maojun Wang
3 and
Jin Wei
3
1
Beijing Institute of Smart Energy, Beijing 102209, China
2
Beijing Huairou Laboratory, Beijing 101409, China
3
The School of Integrated Circuits, Peking University, Beijing 100871, China
4
The College of Microelectronics, Beijing University of Technology, Beijing 100124, China
*
Author to whom correspondence should be addressed.
Electronics 2024, 13(9), 1701; https://doi.org/10.3390/electronics13091701
Submission received: 15 March 2024 / Revised: 12 April 2024 / Accepted: 17 April 2024 / Published: 28 April 2024
(This article belongs to the Special Issue Wide Bandgap Semiconductor: From Epilayer to Devices)
Browse Figures
Versions Notes

Abstract

:
A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.

1. Introduction

With the increasing energy demand and growing environmental concerns, the application of power electronics in the energy sector is becoming increasingly important. Modern power electronics continues to evolve towards a high power, high efficiency, and integration [1]. Power semiconductor devices play a crucial role in this development.
Over the past few decades, the rapid progress of power semiconductor devices has primarily relied on the advancement of silicon-based devices [2]. Silicon, with its ability to undergo thermal oxidation and form silicon dioxide, is an excellent insulator suitable for producing stable metal-oxide-semiconductor (MOS) devices [3]. However, traditional silicon-based power MOSFETs face challenges in effectively operating in high-temperature, high-power, and high-frequency applications due to the inherent limitations of silicon’s physical properties. In contrast, wide-bandgap semiconductor materials like gallium nitride (GaN) and silicon carbide (SiC) exhibit superior physical characteristics, including a high breakdown field and high electron mobility, making them ideal for future power devices [4].
Among the wide-bandgap materials, the commercial application of SiC materials is the most mature. SiC MOSFETs emerge as an excellent candidate for replacing silicon-based MOSFETs in the next generation of power electronic systems. The carbonization of silicon carbide enables it to undergo thermal oxidation, similar to silicon, which are considered as a promising approach to enhance the performance of the next-generation power conversion systems [5,6].
The development of SiC MOSFETs is hindered by its low channel mobility which leads to a large channel resistance [7,8]. There are many techniques being reported for the reduction of the channel resistance, such as the adoption of a shorter channel, MOS interface treatment for a higher channel mobility, etc. [9,10,11,12,13]. Among the efforts, the trench MOSFET structure is widely recognized as a promising approach for realizing a low-resistance SiC power transistor, since it allows a more compact cell design, and, thus, lowers the channel resistance by increasing the channel density [14,15]. Moreover, the trench MOSFET structure presents the flexibility to exploit the higher channel mobility on non-basic faces [16,17,18].
For conventional trench MOSFETs, there is no shielding region, and, for this reason, the devices may face many problems upon high drain voltage. One of the problems is the high OFF-state oxide field at the trench corner. Although the breakdown field of oxide in SiC MOSFETs (typically more than 10 MV/cm [19]) is significantly higher than that of SiC, it is supposed to keep the maximum oxide electric field (EOX-M) below 3 MV/cm for long-term reliability [20,21]. Furthermore, the presence of a large reverse transfer capacitance significantly hampers the switching performance of conventional trench MOSFETs, resulting in an unsatisfactory operation [13]. To solve these problems, in 1998, J. Tan et al. proposed the use of a p-shield region beneath the trench gate as a means of oxide protection. This device demonstrated a breakdown voltage (BV) of 1400 V at an oxide field of 3.1 MV/cm. However, the potential dynamic issues associated with the floating p-type shielding region were overlooked. In a subsequent study conducted by J. Wei et al. from the Hong Kong University of Science and Technology, it was discovered that the p-shield region needs to be properly grounded in order to fully exploit the dynamic characteristics of the devices [22]. In 2017, Dethard Peters et al. described an asymmetric SiC trench MOSFET concept (Asym-MOS), with a well-grounded p-shield region on one side and the bottom of the gate in a cell to shield the gate oxide [23]. The most favorable orientation was chosen for improving the channel mobility and the results show that the channel mobility for the selected crystal plane is twice as large as the traditional crystal plane [24,25]. However, the implementation of this structure entails stringent fabrication requirements for the trenches. In 2020, T. Yang et al. from Tsinghua University introduced a novel SiC trench MOSFET design featuring deep p+ shielded regions and current spreading layers (CSLs) (referred to as DPCSL-MOS) [26]. The findings demonstrate that incorporating CSLs with a higher doping concentration than the drift layer effectively mitigates the JFET effect and reduces the resulting device ON-resistance (RON). The device shows a BV of 1560 V with a RON of 1.72 mΩ·cm2 because of the high channel mobility of 50 cm2/V-s being adopted. However, the complexity of the device fabrication process, which includes secondary epitaxial growth, poses challenges for its current commercialization. In 2023, J. Gao et al. described a recessed source trench silicon carbide MOSFET with integrated MOS-channel diode (MCD) [27]. The MCD utilizes a short channel with adjustable length by varying the recessed depth. This design eliminates the bipolar degradation of the parasitic body p-i-n diode by creating a low potential barrier for the electron flow through the JFET region. The recessed source trench introduces an additional depletion region, resulting in a more uniform distribution of the OFF-state electric field. As a result, the proposed SiC MOSFET achieves a significant reduction in the gate-to-drain capacitance and an improvement in thebreakdown voltage compared to the SiC trench MOSFET with an integrated self-assembled three-level protection Schottky barrier diode. However, the current process still involves multiple etching and implantation steps, suggesting that further technological advancements are needed.
In this work, a SiC fin-channel MOSFET (Fin-MOS) is proposed to enhanced the gate shielding effect, and is comprehensively investigated using TCAD simulations. Grounded p-shield regions are placed under the gates to reduce the gate-to-drain electrical coupling. The manufacturing process of the proposed Fin-MOS is compatible with the traditional trench MOSFET. However, the ohmic contact to the p-base is removed because of the narrow fin-channel region. As reported in the literature [22], a floating p-region may result in instabilities due to the charge storage effect. In this work, we proposed a Fin-MOS structure model with the parasitic n-p-n structure to investigate the threshold voltage instability of the Fin-MOS. It is found that, in the proposed Fin-MOS, as a result of the enhanced shielding effect, the charge-storage-induced instability is negligible. Compared to the conventional trench MOSFET and asymmetric trench MOSFET, the proposed Fin-MOS exhibits the lowest EOX-M to 0.77 MV/cm while maintaining a low ON-resistance (RON). Moreover, the Fin-MOS boasts the lowest reverse transfer capacitance (Crss), gate charge (QG), gate-to-drain charge (QGD), and saturation current (Isat) among these three structures. As a result, the adoption of the Fin-MOS structure holds significant promise in the development of high-performance SiC power switching transistors. By utilizing the Fin-MOS design, the dynamic stability of devices in high-voltage switch applications can be improved. This advancement offers a potential solution to enhance the overall performance and reliability of SiC-based power switches.

2. Device Structure and Parameter Optimization

2.1. Simulation Models

This study employs numerical simulations using Sentaurus TCAD to investigate the topic under consideration. The electron/hole continuity equations and Poisson equation are solved self-consistently, incorporating various factors, including the Shockley–Read–Hall recombination, Auger recombination, incomplete dopant ionization, doping-dependent transport, band narrowing, anisotropic material properties, and impact ionization [28]. The electron and hole impact ionization coefficients described in [10] are implemented in this study. The simulation parameters for the Trench-MOS are formulated based on the methodology outlined in Reference [9], while those for the Asym-MOS are derived from Reference [23]. It is important to note that specific parameters for the Asym-MOS have not been publicly disclosed by Infineon, which may result in deviations between the simulated Asym-MOS devices and their real commercial counterparts. Nevertheless, all parameters, except those discussed in the paper that require optimization, remain consistent with the Trench-MOS to facilitate meaningful comparisons.

2.2. Structure

Figure 1 shows the cross-sectional structures of the Trench-MOS, the Asym-MOS, and the proposed Fin-MOS. The devices studied in this letter are designed to work below 1200 V. For all of the devices, the doping concentration of the drift region is 8 × 1015 cm−3 and the thickness (from the bottom of the gate to the backside n+ region) is 11 μm. The depth of the gate trench is set to 1.5 μm. For both the sidewall and the bottom, the thickness of the gate oxide is 50 nm. The length of the channels is 0.5 μm. The channel mobility of the Trench-MOS and the Fin-MOS is set to 20 cm2/V-s [29,30,31,32,33]; the channel mobility of the Asym-MOS will be discussed later. For the Fin-MOS, the fin-width is Wfin. The cell-width (Wcell) of the Trench-MOS, the Asym-MOS, and the Fin-MOS are, respectively, 3 μm, 2.7 μm, and 3 μm + Wfin.

2.3. Fabrication

For the Trench-MOS and the Asym-MOS, the fabrication technologies are well-established. For the proposed Fin-MOS, the fabrication process is shown in Figure 2. As shown in Figure 2a, the epitaxial structure consists of the n+ substrate, a 10.8 μm n-drift region with a doping concentration of 8 × 1015 cm−3, and a 1.8 μm n-type JFET region (in this region, while the p-type shielding regions on both sides and the n-type region in the middle form a structure similar to the Junction Field-Effect Transistor (hence the name JFET region), with a doping concentration of NJFET, and, at the top, is a 0.7 μm p-type layer with a doping concentration of NPB used as the base region. The device fabrication commented with multiple nitrogen implantations to form the n+ source region as shown in Figure 2b. Then, the inductively coupled plasma reactive ion etching (RIE) is used to form the gate trench, as illustrated in Figure 2c. Then, multiple implantations are utilized to form the p+ shield region, as shown in Figure 2d. The self-aligned process is recommended to simplify the fabrication process. The offset distance between the p-shield and trench corner (Woff) is 0.2 μm. As shown in Figure 2e, Spacer-gate technology can be used to form the gates. The final process included the deposition of the gate oxide and the metal overlay process, which are shown in Figure 2f.

2.4. Parameter Optimization

All three devices have different structural configurations, resulting in inconsistent cell widths. For the Trench-MOS, all the parameters are constant. For the proposed Fin-MOS, Wfin is a key factor affecting device performance, and it is also the first parameter we need to determine. On this basis, it is necessary to further determine the doping concentration in the base region. For the Asym-MOS and Fin-MOS devices, which feature shielded regions, the doping concentrations in the JFET regions will be optimized. Furthermore, in terms of channel mobility in the simulation, we did not set the mobility of the Asym-MOS the same as the other two types of MOSFETs, as previous studies have reported that a channel along the (11–20) face exhibits approximately twice the channel mobility (μch) compared to that along the (−1–120) face [24,25].
Figure 3a presents the influence of Wfin upon BV in the proposed Fin-MOS. For the conventional SiC MOSFET, the p-base typically has a doping level of ~1017 cm−3. Using a narrow fin-structure, junction-less MOSFETs without p-base doping (NPB) are proven to be possible [34,35]. However, for NPB = 0 cm−3, BV is very sensitive to Wfin, and drops quickly at a relatively small Wfin because the p-base is easily punched through. With NPB = 1017 cm−3, BV is more robust, and drops more gently with Wfin. In this work, Wfin = 0.2 μm is adopted for a robust BV.
The doping of the p-base may influence the devices’ threshold voltage [14,36]. As shown in Figure 3b, the devices’ threshold voltage (Vth) increases with the increase in NPB, and gradually saturates for NPB beyond 1017 cm−3. In this work, NPB = 1 × 1017 cm−3 is adopted.
For the proposed Fin-MOS, the JFET region between the adjacent p-shield regions may result in a large resistance if improperly designed. Figure 3c presents RON of the Fin-MOS as a function of NJFET. RON decreases with NJFET, and becomes insensitive for NJFET beyond 1017 cm−3. Therefore, NJFET = 1 × 1017 cm−3 is adopted in the remaining part of the paper.
For the Asym-MOS, NJFET is to be optimized. With the increasing of NJFET, the depletion regions around the p-shields gradually shrink and results in a lower RON, but the shielding effect becomes weaker, which leads to a higher EOX-M. Figure 4a shows the effects of NJFET on RON and EOX-M. RON is obtained at VGS = 15 V. EOX-M is obtained at VGS = 0 V and VDS = 1200 V. In this work, NJFET = 5 × 1016 cm−3 is adopted. For the Asym-MOS, the orientation of the trench channel can be adjusted in the etching process. It is reported a channel along the (11–20) face results in a channel mobility (μch) around twice of that along the (−1–120) face [24,25]. Figure 4b shows the influence of μch upon RON. With μch increasing from 20 cm2/V-s to 40 cm2/V-s, the RON of Asym-MOS decreases from 1.98 mΩ·cm2 to 1.72 mΩ·cm2. In the remaining part of the paper, the μch of Trench-MOS and Fin-MOS is set to 20 cm2/V-s, while the μch of Asym-MOS is set to 40 cm2/V-s.

3. Investigation of Threshold Voltage Instability

As reported in the literature, a floating p-region inside a SiC MOSFET might store negative charges upon high drain voltage stress, resulting in dynamic performance instabilities [22]. As shown in Figure 5a, for the proposed Fin-MOS, the p-base is a floating p-region, and the potential negative charge storage upon high drain voltage might lead to a positive threshold voltage shift (∆Vth), as observed in GaN power transistors with a floating p-region [37,38]. However, the Fin-MOS with a small Wfin may not face this problem because the narrow JFET region is supposed to provide a strong shielding effect to the floating p-base. To prove this, for devices with a different Wfin, dynamic I–V simulation is carried out using the testing waveforms in Figure 5b. A high drain voltage pulse is applied to the device to mimic the OFF-state stress in switching applications. Then, 1 μs after the drain pulse, the VGS sweeps from 0 to 15 V for the dynamic transfer measurement, and the dynamic Vth is extracted. Figure 5c shows the influence of Wfin upon ∆Vth. When the Wfin is larger than 1 μm, ∆Vth increases sharply.
Figure 5d illustrates the charge storage process in the floating p-base of the Fin-MOS. Upon high VDS, the p-n junction formed by the p-base and its upper n-region turns on, and holes will be injected into the upper n-region. After the high VDS is removed, the holes cannot flow back to the p-base, leaving net negative charges, and causing a dynamic threshold voltage drift.
The above analysis can be further reflected and proven by the changes in the voltage of the floating p-region (VPB). Figure 5e shows the simulated waveforms of VPB of two devices with Wfin = 1.2 μm and 0.2 μm. When Wfin = 1.2 μm, VPB rises to 2.8 V as VDS is swept from 0 V to 800 V, which turns on the p-n junction; therefore, holes are injected out of the p-base. After the drain pulse, VPB drop to −0.72 V, which proves the storage of net negative charges in the p-base. However, the charge storage effect is not observed for the device with Wfin = 0.2 μm, since the p-base is well-shielded. Figure 5f plots VPB at 399 μs (immediately after drain pulse) as a function of Wfin. When Wfin is larger than 1 μm, VPB becomes negative. The result agrees with Figure 5c. Therefore, for the Fin-MOS with Wfin = 0.2 μm, the charge storage effect and the consequent dynamic threshold voltage shift are negligible.

4. Device Characteristics

Figure 6 shows the I–V characteristics of the three SiC MOSFETs. The Trench-MOS boasts the lowest RON of 1.61 mΩ·cm2 because of the high channel density. The Asym-MOS has a much lower channel density than the Trench-MOS, and it still has a low RON of 1.72 mΩ·cm2 because of the high channel mobility of 40 cm2/V-s being adopted. Though a low channel mobility of 20 cm2/V-s is being adopted, the Fin-MOS has a low RON of 1.71 mΩ·cm2, owing to the high channel density. The slight increase in RON compared to the Trench-MOS is caused by the JFET resistance when the current passes though the aperture between p-shields. All the studied MOSFETs present a breakdown voltage beyond 1500 V. The Fin-MOS boasts the highest breakdown voltage because the distances beyond p-shield regions are reduced, which smooths the electric field distribution. Furthermore, though with a higher channel density than the Asym-MOS, the saturation current of the Fin-MOS is the lowest among the three, as a result of its narrow JFET region.
Figure 7 shows the OFF-state electric field distributions at VDS = 1200 V in a half-cell of the studied MOSFETs. For the Trench-MOS, EOX-M at the trench corner is as high as 7.43 MV/cm, which puts a severe threat to the device’s long-term reliability. For the Asym-MOS, EOX-M drops down to 1.45 MV/cm with the shielding effect by the grounded p-shield regions. For the proposed Fin-MOS, because of its narrow JFET region, the gate shielding effect is strengthened so that the EOX of 0.77 MV/cm is lower than that in the Asym-MOS.
Reverse transfer capacitance (Crss) is one of the important dynamic characteristics of the power devices [39,40]. Figure 8 shows the Crss of the three SiC MOSFETs. The Trench-MOS suffers the largest Crss. For the Asym-MOS, the p-shield regions provide a shield to the gate, resulting in a lower Crss. For the proposed Fin-MOS with Wfin = 0.2 μm, the p-shield provides the strongest shield to the gate, leading to the lowest Crss among the studied MOSFETs.
Figure 9 shows the VGS–QG curves of the three SiC MOSFETs. The test circuit is shown in Figure 9b. For 1200 V devices, the operating range of VDS typically falls within 0–800 V [9,16]; for the Trench-MOS, it is QG = 2093 nC/cm2 and QGD = 1063 nC/cm2; for the Asym-MOS, it is QG = 1424 nC/cm2 and QGD = 107 nC/cm2; while, for the Fin-MOS, it is QG = 1282 nC/cm2 and QGD = 62 nC/cm2. For comparison, the main characteristics of the three SiC MOSFETs are listed in Table 1. The Fin-MOS boasts the highest breakdown voltage and the lowest EOX-M, Crss, QG, QGD, and Isat. At the same time, the Fin-MOS achieves a comparable low RON.
Additionally, to demonstrate the advantages of the proposed SiC fin-channel MOSFET, the dynamic and static figures of merit (FOMs) for the three devices are shown in Table 1. It is found that the proposed Fin-MOS exhibits the highest static FOM and the lowest dynamic FOM, further highlighting its favorable characteristics.

5. Conclusions

For conventional trench MOSFETs, there is no shielding region and, for this reason, the devices may face many problems upon high drain voltage. In this work, a SiC fin-channel MOSFET (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. Sentaurus TCAD simulations are carried out to optimize the parameters. For the Fin-MOS, Wfin = 0.2 μm is adopted for a robust BV. Then, NPB = 1 × 1017 cm−3 is adopted because Vth increases with the increase in NPB, and gradually saturates for NPB beyond 1017 cm−3. Finally, NJFET = 1 × 1017 cm−3 is adopted because RON decreases with NJFET, and becomes insensitive for NJFET beyond 1017 cm−3. For the Asym-MOS, NJFET = 5 × 1016 cm−3 is adopted and μch is set to 40 cm2/V-s.
For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base. However, a floating p-base might potentially store negative charges upon high drain voltage and, thus, causes threshold voltage instabilities. In this work, we proposed a Fin-MOS structure model with the parasitic n-p-n structure to investigate the threshold voltage instability of the Fin-MOS. With the help of a simulation, we revealed, in the proposed Fin-MOS with Wfin = 0.2 μm, as a result of the enhanced shielding effect, the charge storage induced instability is negligible. However, when Wfin is larger than 1 μm, devices will still face the problem of threshold voltage instabilities.
Finally, the static and dynamic characteristics of the three devices were characterized. Compared to the conventional trench MOSFET (Trench-MOS) and the asymmetric trench MOSFET (Asym-MOS), the Fin-MOS boasts the best OFF-state characteristic, and the lowest reverse transfer capacitance and saturation current. Moreover, the Fin-MOS keeps a similar low ON-resistance. Therefore, the Fin-MOS is a promising approach to realize high-performance and SiC power-switching transistors and help to improve the dynamic stability of devices in high-voltage switch applications.

Author Contributions

Conceptualization, L.S.; methodology, R.J.; validation, L.S.; formal analysis, R.J.; investigation, L.S., R.J., J.C., X.N., Z.L., J.Y., M.N., M.Z., M.W. and J.W.; writing—original draft, J.C.; writing—review and editing, L.S., R.J., X.N., Z.L., J.Y., M.Z., M.W. and J.W. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

The data are contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Schematic cross-sectional structures of (a) the conventional trench MOSFET (Trench-MOS), (b) the asymmetric trench MOSFET (Asym-MOS), and (c) the proposed fin-channel MOSFET (FinMOS).
Figure 1. Schematic cross-sectional structures of (a) the conventional trench MOSFET (Trench-MOS), (b) the asymmetric trench MOSFET (Asym-MOS), and (c) the proposed fin-channel MOSFET (FinMOS).
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Figure 2. The fabrication process for the Fin-MOS. (a) Forming the first epi layer. (b) Forming the n+ source region. (c) Forming the gate trench. (d) Forming the p-shield region. (e) Spacer-gate technology is used to form the gates. (f) Forming the gate oxide and metal overlay.
Figure 2. The fabrication process for the Fin-MOS. (a) Forming the first epi layer. (b) Forming the n+ source region. (c) Forming the gate trench. (d) Forming the p-shield region. (e) Spacer-gate technology is used to form the gates. (f) Forming the gate oxide and metal overlay.
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Figure 3. (a) The influence of Wfin upon BV for different NPB (NJFET = 1 × 1017 cm−3) in Fin-MOS. Wfin = 0.2 μm is chosen as the optimized value. (b) The influence of NPB upon Vth (NJFET = 1 × 1017 cm−3) in Fin-MOS (VDS = 1 V). NPB = 1 × 1017 cm−3 is chosen as the optimized value. (c) The influence of NJFET upon RON for different NPB (VGS = 15 V). NJFET = 1 × 1017 cm−3 is chosen as the optimized value.
Figure 3. (a) The influence of Wfin upon BV for different NPB (NJFET = 1 × 1017 cm−3) in Fin-MOS. Wfin = 0.2 μm is chosen as the optimized value. (b) The influence of NPB upon Vth (NJFET = 1 × 1017 cm−3) in Fin-MOS (VDS = 1 V). NPB = 1 × 1017 cm−3 is chosen as the optimized value. (c) The influence of NJFET upon RON for different NPB (VGS = 15 V). NJFET = 1 × 1017 cm−3 is chosen as the optimized value.
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Figure 4. (a) The trade-off between RON and EOX-M (μch = 40 cm2/Vs) in Asym-MOS. NJFET = 5 × 1016 cm−3 is chosen as the optimized value for the study in the remaining part of the letter. (b) The influence of μch upon RON in Asym-MOS.
Figure 4. (a) The trade-off between RON and EOX-M (μch = 40 cm2/Vs) in Asym-MOS. NJFET = 5 × 1016 cm−3 is chosen as the optimized value for the study in the remaining part of the letter. (b) The influence of μch upon RON in Asym-MOS.
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Figure 5. Investigation of threshold voltage instability of the Fin-MOS. (a) The Fin-MOS structure with the parasitic n-p-n structure highlighted. (b) Testing waveforms for the dynamic I–V simulations. (c) The simulated ∆Vth (Vth after 800 V drain pulse minus Vth after 0 V drain pulse) as a function of Wfin. (d) Illustration of the charge storage effect in floating p-base. (e) VPB waveforms for Fin-MOS with Wfin = 1.2 μm and Fin-MOS with Wfin = 0.2 μm. (f) The influence of Wfin upon VPB.
Figure 5. Investigation of threshold voltage instability of the Fin-MOS. (a) The Fin-MOS structure with the parasitic n-p-n structure highlighted. (b) Testing waveforms for the dynamic I–V simulations. (c) The simulated ∆Vth (Vth after 800 V drain pulse minus Vth after 0 V drain pulse) as a function of Wfin. (d) Illustration of the charge storage effect in floating p-base. (e) VPB waveforms for Fin-MOS with Wfin = 1.2 μm and Fin-MOS with Wfin = 0.2 μm. (f) The influence of Wfin upon VPB.
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Figure 6. The I–V characteristics of the three SiC MOSFETs.
Figure 6. The I–V characteristics of the three SiC MOSFETs.
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Figure 7. The OFF-state electric field distributions at VDS = 1200 V in a half-cell of (a) the Trench-MOS, a cell of (b) the Asym-MOS, and a half cell of (c) the Fin-MOS.
Figure 7. The OFF-state electric field distributions at VDS = 1200 V in a half-cell of (a) the Trench-MOS, a cell of (b) the Asym-MOS, and a half cell of (c) the Fin-MOS.
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Figure 8. Reverse transfer capacitance (Crss) of the studied MOSFETs.
Figure 8. Reverse transfer capacitance (Crss) of the studied MOSFETs.
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Figure 9. (a) VGS–QG curves of the studied MOSFETs. (b) The test circuit for the gate charge characteristics. For the Trench-MOS, QG = 2093 nC/cm2 and QGD = 1063 nC/cm2, for the Asym-MOS, QG = 1424 nC/cm2 and QGD = 107 nC/cm2, while, for the Fin-MOS, QG = 1282 nC/cm2 and QGD = 62 nC/cm2.
Figure 9. (a) VGS–QG curves of the studied MOSFETs. (b) The test circuit for the gate charge characteristics. For the Trench-MOS, QG = 2093 nC/cm2 and QGD = 1063 nC/cm2, for the Asym-MOS, QG = 1424 nC/cm2 and QGD = 107 nC/cm2, while, for the Fin-MOS, QG = 1282 nC/cm2 and QGD = 62 nC/cm2.
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Table 1. Characteristic of the Trench-MOS, the Asym-MOS, and the Fin-MOS.
Table 1. Characteristic of the Trench-MOS, the Asym-MOS, and the Fin-MOS.
Trench-MOSAsym-MOSFin-MOSUnit
μch204020cm2/Vs
RON a1.611.721.71mΩ·cm2
BV159715861814V
Static FOM b158414621924MW/cm2
EOX-M c7.431.450.77MV/cm
Vth5.175.133.22V
Isat d14.098.256.56KA/cm2
Crss e67819.83.1pF/cm2
QG209314241282nC/cm2
QGD106310762nC/cm2
Dynamic FOM f1711184106mΩ·nC
a RON at VGS = 15 V. b BV2/RON. c EOX-M at VDS = 1200 V. d Isat at VDS = 800 V. e Crss at VDS = 600 V. f QGD·RON.
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Sang, L.; Jin, R.; Cui, J.; Niu, X.; Li, Z.; Yang, J.; Nuo, M.; Zhang, M.; Wang, M.; Wei, J. SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect. Electronics 2024, 13, 1701. https://doi.org/10.3390/electronics13091701

AMA Style

Sang L, Jin R, Cui J, Niu X, Li Z, Yang J, Nuo M, Zhang M, Wang M, Wei J. SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect. Electronics. 2024; 13(9):1701. https://doi.org/10.3390/electronics13091701

Chicago/Turabian Style

Sang, Ling, Rui Jin, Jiawei Cui, Xiping Niu, Zheyang Li, Junjie Yang, Muqin Nuo, Meng Zhang, Maojun Wang, and Jin Wei. 2024. "SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect" Electronics 13, no. 9: 1701. https://doi.org/10.3390/electronics13091701

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