Influence Analysis of SiC MOSFET’s Parasitic Capacitance on DAB Converter Output

Abstract

This paper proposes the influence analysis of silicon carbide (SiC) MOSFET’s parasitic output capacitance on a dual active bridge (DAB) converter. Power converters are required for DC grids and energy storage. Because SiC metal-oxide-semiconductor FETs (MOSFETs) have lower on-state resistance and faster reverse recovery time than Si MOSFETs, they can be controlled with lower losses and higher frequencies. MOSFETs have a parasitic capacitance. Because of the output parasitic capacitance, the switch voltage does not rise instantaneously during switching but has a delay. The output parasitic capacitance of the switch depends on its drain-to-source voltage, and this parasitic capacitance affects the output of the DAB converter by delaying the switch voltage. In this paper, in order to analyze the effect of the parasitic capacitance on the DAB converter output, the delay time was calculated through a formula, and this value was compared with a simulated value. In addition, the effect of the parasitic capacitance of the SiC MOSFET on the output of the DAB converter was presented by comparing the actual output voltage with the ideal output voltage and analyzing the effect of the output voltage according to the delay.

1. Introduction

Recently, interest in renewable energy, electric vehicles, and microgrids has increased owing to environmental issues and carbon-neutral policies. DC power is increasing owing to the increase in renewable energy sources, and the number of devices using DC is also increasing; therefore, the demand for DC power distribution and energy storage is increasing. Power converters, such as bidirectional DC–DC converters, are required for DC grids and energy storage [1,2,3,4].

Dual active bridge (DAB) converters have been proposed for high-power density high-power conversion systems [5,6,7], and many studies have been conducted because of the advantage of performing bidirectional power transfer with a simple structure [8]. A DAB converter consists of a full-bridge switch across a high-frequency transformer. It has full-bridge switches at both ends, transmits power using the leakage inductance of the transformer, and uses a series inductor to obtain the necessary inductance [5,9].

The DAB converter transfers power bidirectionally by using the phase shift between the primary and secondary side switches. Switches use metal–oxide–semiconductor field effect transistors (MOSFETs) or insulated-gate bipolar transistors [10,11]. A high switching frequency is required for high-efficiency, high-density power conversion. Silicon carbide (SiC) MOSFETs, which are SiC-based power semiconductors, have attracted attention as next-generation semiconductors, along with gallium-nitride-based power semiconductors [12,13]. They have a higher breakdown voltage than conventional Si-based switches but a low loss because of their low on-resistance (${\mathrm{R}}_{\mathrm{DS}\left(\mathrm{ON}\right)}$) and excellent heat dissipation characteristics, so it is possible to achieve high system efficiency and density using high frequencies [14].

The phase control of the DAB converter uses single-phase-shift (SPS) control for ease of control. The SPS method also helps achieve zero-voltage switching (ZVS) over a wide area when the input/output voltage ratio is 1 [15,16,17,18].

A MOSFET has a structure in which an oxide film and a PN junction are formed, and a diode is embedded. Parasitic capacitance exists between the gate, drain, and source owing to the capacitances of the oxide film and PN junction. This parasitic capacitance affects electromagnetic emission and the drain–source voltage rise and fall times [19]. Parasitic capacitors cause switch turn-on and turn-off transients and considerably increase switching energy losses [20]. Additionally, improved dynamic performance is required when controlling power flow in aerospace applications [21,22].

Therefore, in this paper, the effect of parasitic capacitance on the output is analyzed when the DAB converter is controlled by the commonly used SPS method. First, an equation for calculating the delay time of switch voltage change caused by parasitic capacitance and leakage reactance resonance is presented, and the results are compared with the result of the simulation. In addition, the effect of the parasitic capacitance on the DAB output is compared and analyzed through simulation and experiment. The results analyzed through this paper can be applied as considerations for precisely controlling DAB and reducing loss.

Section 2 describes the DAB converter operating characteristics. Section 3 discusses the parasitic capacitance of switches. Section 4 reports the switch parasitic capacitance analysis simulation results and experimental results. Section 5 presents the conclusion.

2. Operation Characteristics of DAB Converter

Figure 1 shows a DAB converter circuit. The DAB converter is an isolated bidirectional DC–DC converter that consists of a full-bridge switch and an additional series inductor across a high-frequency transformer. All switches of the DAB converter use a 50% duty ratio and transfer bidirectional power using the phase shift ($\mathsf{\varphi }$) between the primary and secondary side voltages [23]. If the phase of the primary side is faster than that of the secondary side, power is transferred from the primary to the secondary side. If the phase of the secondary side is faster, power is transferred from the secondary to the primary side. The voltage difference caused by the phase shift is applied to the inductor, which stores energy and delivers power based on the phase shift.

Figure 2 shows the operating waveform according to the SPS switch control of the DAB converter [5]. The SPS control method is widely used as the simplest method for transferring power with only a phase shift between the primary- and secondary-side switches.

3. Parasitic Capacitance of Switches

Figure 3 shows the parasitic components of the MOSFET. In MOSFETs, the gate, drain, and source are insulated by an oxide film, and there is a freewheeling diode between the drain and source. When the switch is off, the energy stored in the inductor flows through the freewheeling diode. The parasitic components are divided into the input parasitic capacitance (${\mathrm{C}}_{\mathrm{iss}}={\mathrm{C}}_{\mathrm{gs}}+{\mathrm{C}}_{\mathrm{gd}}$), output parasitic capacitance (${\mathrm{C}}_{\mathrm{oss}}={\mathrm{C}}_{\mathrm{ds}}+{\mathrm{C}}_{\mathrm{gd}}$), and return parasitic capacitance (${\mathrm{C}}_{\mathrm{rss}}={\mathrm{C}}_{\mathrm{gd}}$). Because of the parasitic capacitance, the voltage across the switch does not instantaneously rise or fall during switching but changes with a delay owing to the effect of the parasitic capacitance.

Figure 4 shows the equivalent circuit according to the switching operation of the DAB converter when the parasitic capacitance in the SiC MOSFET is considered. The full-bridge switch of the DAB converter operates in a complementary manner. If the switches of the legs are turned on at the same time, the switches can burn out and have dead time. During the dead time, all switches are turned off, and the parasitic capacitance of the switch is charged and discharged because of the energy stored in the inductor in the previous state. The parasitic capacitors of switches Q2 and Q3 are charged such that the voltage across the switch becomes equal to the input voltage. The parasitic capacitors of switches Q1 and Q4 are discharged, the diode is turned on, and the voltage across the switch is kept close to 0 V. With this operation, the DAB converter achieves ZVS.

In the equivalent circuit in Figure 4b, during dead time, the output capacitance (${\mathrm{C}}_{\mathrm{Q}}$) of the SiC MOSFET is in series resonance with the leakage inductance (${\mathrm{L}}_{\mathrm{L}}$), and the resonance frequency (${\mathrm{f}}_{\mathrm{r}}$) is as follows.

$${\mathrm{f}}_{\mathrm{r}}=\frac{1}{2\mathsf{\pi }\sqrt{{\mathrm{L}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{Q}}}}$$

(1)

The current flowing by the leakage inductance charges and discharges the parasitic capacitance of the switching element during the dead time. When all the parasitic capacitances of the switching elements are the same and the loss is ignored, the relationship between the current (${\mathrm{I}}_{\mathrm{L}}$) flowing through the leakage inductance and the current (${\mathrm{I}}_{\mathrm{C}}$) flowing through the parasitic capacitance is as follows.

$${\mathrm{I}}_{\mathrm{L}}=\frac{1}{2}{\mathrm{I}}_{\mathrm{C}}$$

(2)

The energy stored in the leakage inductance must be equal to or greater than the energy required to charge and discharge the parasitic capacitance during the dead time for ZVS operation. Therefore, the relationship between the energy stored by the leakage inductance and the energy supplied to the parasitic capacitance can be expressed using Equation (3). Here, $\mathrm{K}$ is the number of switches, ${\mathrm{I}}_{\mathrm{Lp}}$ is the peak value of the inductor current, and ${\mathrm{V}}_{\mathrm{Qp}}$ represents the peak value of the voltage across the parasitic capacitance.

$$\frac{1}{2}{\mathrm{I}}_{\mathrm{L}}{\mathrm{I}}_{\mathrm{Lp}}^2\ge \mathrm{K}\frac{1}{2}{\mathrm{C}}_{\mathrm{Q}}{\mathrm{V}}_{\mathrm{Qp}}^2$$

(3)

In the DAB converter, leakage inductance current changes as follows. If the ratio of the primary voltage and the secondary voltage considering the $\mathrm{K}={\mathrm{V}}_{\mathrm{p}}/{\mathrm{nV}}_{\mathrm{s}}$ is set to 1 for the efficiency and wide ZVS range of the DAB converter, Equation (5) becomes 0.

As a result, the change in leakage inductance current is expressed by Equation (4), and the maximum value of leakage inductance current can be expressed by Equation (6).

$$0~\mathsf{\varphi }:{\mathsf{\Delta }\mathrm{I}}_{\mathrm{L}}=\frac{{\mathrm{V}}_{\mathrm{L}}}{{\mathrm{Z}}_{\mathrm{L}}}\mathsf{\varphi },{ \mathrm{V}}_{\mathrm{L}}={\mathrm{V}}_{\mathrm{P}}+{\mathrm{nV}}_{\mathrm{s}}$$

(4)

$$\mathsf{\varphi }~\left(\mathsf{\pi }-\mathsf{\varphi }\right):{\mathsf{\Delta }\mathrm{I}}_{\mathrm{L}}=\frac{{\mathrm{V}}_{\mathrm{L}}}{{\mathrm{Z}}_{\mathrm{L}}}\left(\mathsf{\pi }-\mathsf{\varphi }\right),{ \mathrm{V}}_{\mathrm{L}}={\mathrm{V}}_{\mathrm{p}}-{\mathrm{V}}_{\mathrm{s}}$$

(5)

$${\mathrm{I}}_{\mathrm{LP}}=\frac{{\mathsf{\Delta }\mathrm{I}}_{\mathrm{L}}}{2}=\frac{{\mathrm{V}}_{\mathrm{p}}+{\mathrm{nV}}_{\mathrm{s}}}{{\mathrm{Z}}_{\mathrm{L}}\times 2}\times \mathsf{\varphi }$$

(6)

In general, a DAB converter is configured as a full bridge using four switching elements on the primary side, so a K of 4 is used. Using the above conditions and Equation (3), the parasitic capacitance voltage ${\mathrm{V}}_{\mathrm{Qp}}$ can be obtained as shown in Equation (7).

The parasitic capacitance voltage can be expressed as follows using the resonant frequency of Equation (1) and the peak voltage of Equation (7).

$${\mathrm{V}}_{\mathrm{Qp}}\le \sqrt{\frac{{\mathrm{L}}_{\mathrm{L}}\times {\mathrm{I}}_{\mathrm{LP}}^2}{\mathrm{K}\times {\mathrm{C}}_{\mathrm{Q}}}}=\sqrt{\frac{{\mathrm{L}}_{\mathrm{L}}\times {\mathrm{I}}_{\mathrm{LP}}^2}{4\times {\mathrm{C}}_{\mathrm{Q}}}}$$

(7)

Because the parasitic capacitance voltage is charged up to the input voltage or discharged from the input voltage to 0 during the dead time, when the condition of Equation (9) is applied to Equation (8), the time for the parasitic capacitance voltage to rise can be calculated as in Equation (10). The time in Equation (10) eventually becomes a delay time that impedes the voltage change because the voltage does not change instantaneously and rises for a certain time.

$${\mathrm{V}}_{\mathrm{Q}}={\mathrm{V}}_{\mathrm{Qp}}\sin \left(2{\mathsf{\pi }\mathrm{f}}_{\mathrm{r}}\times \mathrm{t}\right)$$

(8)

$${\mathrm{V}}_{\mathrm{Q}}={\mathrm{V}}_{\mathrm{in}}$$

(9)

$$\mathrm{t}=\frac{{\sin }^{-1}\left(\frac{{\mathrm{V}}_{\mathrm{in}}}{{\mathrm{V}}_{\mathrm{Qp}}}\right)}{2{\mathsf{\pi }\mathrm{f}}_{\mathrm{r}}}$$

(10)

Figure 5 shows the voltage characteristics of the DAB converter according to the delay time. The delay of the primary-side switch voltage decreased the magnitude of the inductor voltage, but the delay of the secondary-side switch voltage increased the magnitude of the inductor voltage. So, area A represents the effect of the primary-side parasitic capacitance on the leakage inductance voltage, and area B appears due to the impact of the secondary-side parasitic capacitance; when both areas are the same, the effect of the voltage delay due to the parasitic capacitance can be compensated.

To satisfy this condition, the delay time due to the secondary-side parasitic capacitance must be the same as the primary-side delay time, and considering the turns ratio, the following conditions can be created.

$${\mathrm{t}}_{\mathrm{p}}=\frac{{\sin }^{-1}\left(\frac{{\mathrm{V}}_{\mathrm{in}}}{{\mathrm{V}}_{\mathrm{Qpp}}}\right)}{2{\mathsf{\pi }\mathrm{f}}_{\mathrm{rp}}}={\mathrm{t}}_{\mathrm{s}}=\frac{{\sin }^{-1}\left(\frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{Qps}}}\right)}{2{\mathsf{\pi }\mathrm{f}}_{\mathrm{s}}}=\frac{{\sin }^{-1}\left(\frac{{\mathrm{V}}_{\mathrm{in}}\times \frac{1}{\mathrm{n}}}{{\mathrm{V}}_{\mathrm{Qpp}}\times \frac{1}{\mathrm{n}}}\right)}{2{\mathsf{\pi }\mathrm{f}}_{\mathrm{s}}}$$

(11)

For ${\mathrm{t}}_{\mathrm{p}}$ and ${\mathrm{t}}_{\mathrm{s}}$ to be equal, ${\mathrm{f}}_{\mathrm{rp}}$ and ${\mathrm{f}}_{\mathrm{rs}}$ must be equal. Using this condition, the optimal size of the secondary parasitic capacitance based on the primary parasitic capacitance or the optimal size of the primary parasitic capacitance based on the secondary parasitic capacitance can be calculated.

$${\mathrm{f}}_{\mathrm{rp}}=\frac{1}{2\mathsf{\pi }\sqrt{{\mathrm{L}}_{\mathrm{L}}\times {\mathrm{C}}_{\mathrm{Qp}}}}={\mathrm{f}}_{\mathrm{rs}}=\frac{1}{2\mathsf{\pi }\sqrt{\frac{1}{{\mathrm{n}}^2}{\mathrm{L}}_{\mathrm{L}}\times {\mathrm{C}}_{\mathrm{Qs}}}}$$

(12)

$${\mathrm{C}}_{\mathrm{Qp}}=\frac{1}{{\mathrm{n}}^2}\times {\mathrm{C}}_{\mathrm{Qs}}{ \mathrm{or} \mathrm{C}}_{\mathrm{Qs}}={\mathrm{n}}^2{\mathrm{C}}_{\mathrm{Qp}}$$

(13)

Figure 6 shows the parasitic capacitance according to the drain–source voltage of the SiC MOSFET used in this study. Considering the operating voltage of the DAB converter, the primary-side switch was a Cree C3M0016120K, and the secondary-side switch was a Cree C3M0030090K. The parasitic capacitance of the MOSFET changes according to the drain–source voltage of the switch, and the parasitic capacitance decreases as the voltage increases.

Table 1. Output parasitic capacitances according to drain–source voltage.

C3M006120K		C3M0030090K
${\mathbf{V}}_{\mathbf{D}\mathbf{S}}$	${\mathbf{C}}_{\mathbf{o}\mathbf{s}\mathbf{s}}$	${\mathbf{V}}_{\mathbf{D}\mathbf{S}}$	${\mathbf{C}}_{\mathbf{o}\mathbf{s}\mathbf{s}}$
13 V	2 nF	8.125 V	1.5 nF
33 V	1 nF	20.625 V	1.1 nF
133 V	0.5 nF	83.125 V	0.4 nF

lists the output parasitic capacitances of the switch according to the input and output voltages of the DAB converter. To analyze the effect of parasitic output capacitance, 2 times and 0.5 times of parasitic capacitance were selected based on 1 nF. It was configured based on the voltages when the parasitic capacitances of the primary-side switch were 2, 1, and 0.5 nF [24,25].

4. Effect Analysis of Switch Parasitic Capacitance through Simulation and Experiment

Figure 7 shows the DAB converter simulation circuit, which was configured considering the dead time and parasitic capacitance of the switch.

Table 2. DAB converter specification.

Parameter	Symbol	Value
Input voltage	${\mathrm{V}}_{\mathrm{in}}$(V)	13~33
Output voltage	${\mathrm{V}}_{\mathrm{out}}$(V)	8.125~83.125
Switching frequency	${\mathrm{F}}_{\mathrm{SW}}$(kHz)	100
Number of turns	$\mathrm{n}$(turn)	1.6
Leakage inductance	${\mathrm{L}}_{\mathrm{L}}$(uH)	52
Dead time	${\mathrm{D}}_{\mathrm{T}}$(ns)	380
Primary-side output capacitance	${\mathrm{C}}_{\mathrm{Qp}}$(nF)	0.5~2
Secondary-side output capacitance	${\mathrm{C}}_{\mathrm{Qs}}$(nF)	0.4~1.5
Load	${\mathrm{R}}_{\mathrm{Load}}$(Ω)	25

lists the simulation conditions and the output capacitances according to the switch voltages in Table 1.

Figure 8 shows the results based on the simulation conditions. It shows the waveform of the switch of the first leg on the primary side. During the dead time, the energy stored in the inductor in the previous state charges the parasitic capacitance of the switch, and the voltage across the switch increases to the input voltage because of the parasitic capacitance. The voltage does not change instantaneously according to the parasitic capacitance of the switch; however, the parasitic capacitance is charged and delayed. The delay in the rising voltage is affected by the parasitic capacitance, which varies with input voltage. The lower the input voltage, the larger the parasitic capacitance and voltage delay. When the input voltage is 13 V, it has the largest difference compared with the rated output voltage.

Table 3. Delay time calculated using equation.

${\mathbf{V}}_{\mathbf{i}\mathbf{n}}\left[\mathbf{V}\right]$	Calculation Using Equation (10)	Simulation
13	$\mathsf{\varphi }=\frac{\mathsf{\pi }}{\mathbf{2}}\mathbf{\left(}\mathbf{1}\mathbf{-}\sqrt{\mathbf{1}\mathbf{-}\mathbf{\left(}\frac{\mathbf{8}\mathbf{\times }\mathbf{100}\mathbf{k}\mathsf{\times }\mathbf{52}\mathsf{\mu }\mathsf{\times }\mathbf{2.64}}{\mathbf{1.6}\mathsf{\times }\mathbf{13}\mathsf{\times }\mathbf{8.125}}\mathbf{\right)}}\mathbf{\right)}\mathbf{=}\mathbf{0.2042}\mathsf{\pi }$	218 ns
	${\mathbf{f}}_{\mathbf{r}}=\frac{\mathbf{1}}{\mathbf{2}\mathsf{\pi }\sqrt{\mathbf{52}\mathbf{\times }{\mathbf{10}}^{\mathbf{-}\mathbf{6}}\mathbf{\times }\mathbf{2}\mathbf{\times }{\mathbf{10}}^{\mathbf{-}\mathbf{9}}}}\mathbf{=}\mathbf{493}\mathbf{,}\mathbf{518.528}\mathbf{H}\mathbf{z}$
	${\mathbf{I}}_{\mathbf{L}\mathbf{p}}\mathbf{=}\frac{\mathbf{\left(}\mathbf{13}\mathbf{+}\mathbf{1.6}\mathbf{\times }\mathbf{8.125}\mathbf{\right)}\mathbf{\times }\mathbf{0.2042}\mathsf{\pi }}{\mathbf{2}\mathbf{\times }\mathbf{2}\mathsf{\pi }\mathbf{\times }\mathbf{100}\mathbf{k}\mathbf{\times }\mathbf{52}\mathsf{\mu }}\mathbf{=}\mathbf{0.25525}$
	${\mathbf{V}}_{\mathbf{Q}\mathbf{p}}\mathbf{=}\sqrt{\frac{\mathbf{52}\mathbf{\times }{\mathbf{10}}^{\mathbf{-}\mathbf{6}}\mathbf{\times }{\mathbf{0.25525}}^{\mathbf{2}}}{\mathbf{4}\mathbf{\times }\mathbf{2}\mathbf{\times }{\mathbf{10}}^{\mathbf{-}\mathbf{9}}}}\mathbf{=}\mathbf{20.578}$
	$\mathbf{t}\mathbf{=}\frac{{\mathbf{sin}}^{\mathbf{-}\mathbf{1}}\mathbf{\left(}\frac{\mathbf{13}}{\mathbf{20.578}}\mathbf{\right)}\mathbf{\times }\frac{\mathbf{2}\mathsf{\pi }}{\mathbf{360}}}{\mathbf{2}\mathsf{\pi }\mathbf{\times }\mathbf{493}\mathbf{,}\mathbf{518}}\mathbf{=}\mathbf{220.52}\mathbf{n}\mathbf{s}$
33	$\mathrm{t}=\frac{{\sin }^{-1}\left(\frac{33}{73.875}\right)\times \frac{2\mathsf{\pi }}{360}}{2\mathsf{\pi }\times 697,940}=105.59\mathrm{ns}$	106 ns
133	$\mathrm{t}=\frac{{\sin }^{-1}\left(\frac{133}{421.068}\right)\times \frac{2\mathsf{\pi }}{360}}{2\mathsf{\pi }\times 987,037}=51.82\mathrm{ns}$	52 ns

shows a comparison between the delay time calculated using Equation (10) and the delay time measured through the simulation. The delay time calculated using Equation (10) and the time measured through the simulation are almost the same.

Table 4. Simulation results considering parasitic capacitance.

Input Voltage	Ideal Output Voltage	Simulation Output Voltage	Difference
13 V	8.125 V	7.72 V	4.98%
33 V	20.625 V	20.17 V	2.2%
133 V	83.125 V	81.9 V	1.47%

shows the simulation results of the output voltage difference caused by the parasitic capacitance.

Figure 9 shows the experimental configuration used in this study, where three experiments were conducted with input voltages of 13, 33, and 133 V using a DC power supply. An oscilloscope was used to check the operating waveform and input/output voltage, and a power analyzer was used.

Figure 10 shows the waveforms of the experimental results and the voltage waveforms between the high- and low-side gate–source of the first leg of the primary side and the drain–source voltage of the first switch. During the dead time, the voltage of the switch rises to the input voltage, and a delay in the rising voltage appears because of the parasitic capacitance. The lower the voltage input to the switch, the more delay that occurs because of the influence of the output capacitor. The higher the input voltage, the shorter the delay time.

Table 5. Experiment results.

Input Voltage	Ideal Output Voltage	Experiment Output Voltage	Difference
13 V	8.125 V	7.06 V	13.1%
33 V	20.625 V	18.86 V	8.55%
133 V	83.125 V	79.84 V	3.95%

lists the input and output voltages based on the experimental conditions. The lower the input voltage, the greater the difference from the rated output voltage; the higher the input voltage, the smaller the difference.

When DAB is controlled only with the parasitic capacitance of the primary and secondary SiC MOSFETs, the output voltage has an error with the rated value. In order to solve this problem, it is necessary to adjust the first or second value to the size of the optimal parasitic capacitance suggested in the paper.

Table 6. Optimum parasitic capacitance condition.

Input Voltage	${\mathbf{C}}_{\mathbf{Q}\mathbf{p}}$	${\mathbf{C}}_{\mathbf{Q}\mathbf{s}}$	$\mathbf{Optimal} {\mathbf{C}}_{\mathbf{Q}\mathbf{s}}$	$\mathbf{Add} {\mathbf{C}}_{\mathbf{Q}\mathbf{c}}$
13 V	2 nF	1.5 nF	5.12 nF	3.62 nF
33 V	1 nF	1.1 nF	2.56 nF	1.46 nF
133 V	0.5 nF	0.4 nF	1.28 nF	0.88 nF

shows the capacitance additionally required on the secondary side when considering the optimum parasitic capacitance condition.

Figure 11 shows the voltage response characteristics of the DAB converter when the secondary-side parasitic capacitance is set to the optimum capacitance. When the secondary side parasitic capacitance is set to an optimal value, the primary-side delay time and the secondary-side delay time appear identical.

Table 7. Simulation results by optimum parasitic capacitance.

Input Voltage	Ideal Output Voltage	Simulation Output Voltage	Difference
13 V	8.125 V	8.152 V	0.33%
33 V	20.625 V	20.641 V	0.07%
133 V	83.125 V	83.129 V	0.005%

shows the output voltage comparison when set to the optimum parasitic capacitance. When the secondary-side parasitic capacitance is optimally set, there is almost no difference between the secondary-side rated voltage and actual voltage.

5. Conclusions

The output characteristics of the DAB converter were analyzed according to the parasitic capacitance, which varies according to the voltage applied to the switch.

The MOSFET used in the DAB converter has a parasitic capacitance; therefore, the voltage of the switch does not rise instantaneously but rises with a delay. It was confirmed that the output voltage was lower than the rated output voltage owing to the delay in the switch voltage rise. A difference occurred according to the voltage applied to the switch: the larger the parasitic capacitance, the larger the voltage difference.

The experiment confirmed that a maximum voltage difference of 13.1% occurred over the rated output voltage for a 13 V input. It was proved that, in the DAB converter, a difference in output voltage resulting from the parasitic capacitance according to the input voltage occurs, and it must be considered.

Future plans include studying the compensation of the output characteristics owing to the delay in the voltage rise of the switch caused by the parasitic capacitance.